Patchwork Qemu Devel

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Filters: Submitter = Palmer Dabbelt remove filter    |    State = Action Required remove filter    |    Archived = No remove filter
Patch A/R/T Date Submitter Delegate State
[PULL,4/4] default-configs: Enable USB support for RISC-V machines - - - 2019-01-11 Palmer Dabbelt New
[PULL,3/4] RISC-V: Implement existential predicates for CSRs - 1 - 2019-01-11 Palmer Dabbelt New
[PULL,2/4] RISC-V: Implement atomic mip/sip CSR updates - 1 - 2019-01-11 Palmer Dabbelt New
[PULL,1/4] RISC-V: Implement modular CSR helper interface - 1 - 2019-01-11 Palmer Dabbelt New
[PULL,14/14] MAINTAINERS: Mark RISC-V as Supported - 1 - 2018-12-26 Palmer Dabbelt New
[PULL,13/14] riscv/cpu: use device_class_set_parent_realize - 2 - 2018-12-26 Palmer Dabbelt New
[PULL,12/14] target/riscv/pmp.c: Fix pmp_decode_napot() - 1 - 2018-12-26 Palmer Dabbelt New
[PULL,11/14] sifive_uart: Implement interrupt pending register - 2 - 2018-12-26 Palmer Dabbelt New
[PULL,10/14] RISC-V: Enable second UART on sifive_e and sifive_u - 1 - 2018-12-26 Palmer Dabbelt New
[PULL,09/14] RISC-V: Fix PLIC pending bitfield reads - 1 - 2018-12-26 Palmer Dabbelt New
[PULL,08/14] RISC-V: Fix CLINT timecmp low 32-bit writes - 1 - 2018-12-26 Palmer Dabbelt New
[PULL,07/14] RISC-V: Add hartid and \n to interrupt logging - 1 - 2018-12-26 Palmer Dabbelt New
[PULL,06/14] sifive_u: Set 'clock-frequency' DT property for SiFive UART - 1 - 2018-12-26 Palmer Dabbelt New
[PULL,05/14] sifive_u: Add clock DT node for GEM ethernet - 1 - 2018-12-26 Palmer Dabbelt New
[PULL,04/14] riscv: Enable VGA and PCIE_VGA - 1 1 2018-12-26 Palmer Dabbelt New
[PULL,03/14] hw/riscv/virt: Connect the gpex PCIe - 1 2 2018-12-26 Palmer Dabbelt New
[PULL,02/14] hw/riscv/virt: Adjust memory layout spacing - 1 2 2018-12-26 Palmer Dabbelt New
[PULL,01/14] hw/riscv/virt: Increase the number of interrupts - - 2 2018-12-26 Palmer Dabbelt New
[PULL,14/14] MAINTAINERS: Mark RISC-V as Supported - 1 - 2018-12-21 Palmer Dabbelt New
[PULL,13/14] riscv/cpu: use device_class_set_parent_realize - 2 - 2018-12-21 Palmer Dabbelt New
[PULL,12/14] target/riscv/pmp.c: Fix pmp_decode_napot() - 1 - 2018-12-21 Palmer Dabbelt New
[PULL,11/14] sifive_uart: Implement interrupt pending register - 2 - 2018-12-21 Palmer Dabbelt New
[PULL,10/14] RISC-V: Enable second UART on sifive_e and sifive_u - 1 - 2018-12-21 Palmer Dabbelt New
[PULL,09/14] RISC-V: Fix PLIC pending bitfield reads - 1 - 2018-12-21 Palmer Dabbelt New
[PULL,08/14] RISC-V: Fix CLINT timecmp low 32-bit writes - 1 - 2018-12-21 Palmer Dabbelt New
[PULL,07/14] RISC-V: Add hartid and \n to interrupt logging - 1 - 2018-12-21 Palmer Dabbelt New
[PULL,06/14] sifive_u: Set 'clock-frequency' DT property for SiFive UART - 1 - 2018-12-21 Palmer Dabbelt New
[PULL,05/14] sifive_u: Add clock DT node for GEM ethernet - 1 - 2018-12-21 Palmer Dabbelt New
[PULL,04/14] riscv: Enable VGA and PCIE_VGA - 1 1 2018-12-21 Palmer Dabbelt New
[PULL,03/14] hw/riscv/virt: Connect the gpex PCIe - 1 2 2018-12-21 Palmer Dabbelt New
[PULL,02/14] hw/riscv/virt: Adjust memory layout spacing - 1 2 2018-12-21 Palmer Dabbelt New
[PULL,01/14] hw/riscv/virt: Increase the number of interrupts - - 2 2018-12-21 Palmer Dabbelt New
[for-3.1,2/2] MAINTAINERS: Mark RISC-V as Supported - 1 - 2018-11-21 Palmer Dabbelt New
[for-3.1,1/2] MAINTAINERS: Any file with "riscv" in the name is a RISC-V file - - - 2018-11-21 Palmer Dabbelt New
[for-3.2] RISC-V: Deprecate hifive_e and hifive_u machines - - - 2018-11-21 Palmer Dabbelt New
[PULL,4/4] RISC-V: Respect fences for user-only emulators - 2 - 2018-11-16 Palmer Dabbelt New
[PULL,3/4] target/riscv: Fix sfence.vm/a both available in any priv version - 1 - 2018-11-16 Palmer Dabbelt New
[PULL,2/4] target/riscv: Fix FCLASS_D being treated as RV64 only - 1 - 2018-11-16 Palmer Dabbelt New
[PULL,1/4] hw/riscv/virt: Free the test device tree node name - - - 2018-11-16 Palmer Dabbelt New
[PULL,4/4] RISC-V: Respect fences for user-only emulators - 3 - 2018-11-13 Palmer Dabbelt New
[PULL,3/4] target/riscv: Fix sfence.vm/a both available in any priv version - 1 - 2018-11-13 Palmer Dabbelt New
[PULL,2/4] target/riscv: Fix FCLASS_D being treated as RV64 only - 1 - 2018-11-13 Palmer Dabbelt New
[PULL,1/4] hw/riscv/virt: Free the test device tree node name - - - 2018-11-13 Palmer Dabbelt New
[for,3.1] RISC-V: Respect fences for user-only emulators - 2 - 2018-11-09 Palmer Dabbelt New
[0/2] target/riscv: Bugfixes found in decodetree conversion - - - 2018-11-08 Palmer Dabbelt New
[PULL] riscv: spike: Fix memory leak in the board init - 2 - 2018-11-08 Palmer Dabbelt New
[PULL,3/3] Add qemu-riscv@nongnu.org as the RISC-V list - 2 1 2018-11-01 Palmer Dabbelt New
[PULL,2/3] Add Alistair as a RISC-V Maintainer - - - 2018-11-01 Palmer Dabbelt New
[PULL,1/3] target/riscv/pmp.c: pmpcfg_csr_read returns bogus value on RV64 - 2 - 2018-11-01 Palmer Dabbelt New
[PULL,3/3] Add qemu-riscv@nongnu.org as the RISC-V list - 2 1 2018-10-30 Palmer Dabbelt New
[PULL,2/3] Add Alistair as a RISC-V Maintainer - - - 2018-10-30 Palmer Dabbelt New
[PULL,1/3] target/riscv/pmp.c: pmpcfg_csr_read returns bogus value on RV64 - 2 - 2018-10-30 Palmer Dabbelt New
Add qemu-riscv@nongnu.org as the RISC-V list - 2 1 2018-10-30 Palmer Dabbelt New
Add Alistair as a RISC-V Maintainer - 2 - 2018-10-29 Palmer Dabbelt New
[PULL,5/5] RISC-V: Don't add NULL bootargs to device-tree - 3 - 2018-10-17 Palmer Dabbelt New
[PULL,4/5] RISC-V: Add missing free for plic_hart_config - 3 - 2018-10-17 Palmer Dabbelt New
[PULL,3/5] RISC-V: Update CSR and interrupt definitions - 2 - 2018-10-17 Palmer Dabbelt New
[PULL,2/5] RISC-V: Move non-ops from op_helper to cpu_helper - 3 - 2018-10-17 Palmer Dabbelt New
[PULL,1/5] RISC-V: Allow setting and clearing multiple irqs - 2 - 2018-10-17 Palmer Dabbelt New