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Filters: Submitter = Palmer Dabbelt remove filter    |    State = Action Required remove filter    |    Archived = No remove filter
Patch A/R/T Date Submitter Delegate State
sifive_prci: Read and write PRCI registers - 2 - 2019-03-22 Palmer Dabbelt New
target/riscv: Zero extend the inputs of divuw and remuw - 1 - 2019-03-21 Palmer Dabbelt New
[PULL,19/19] riscv: sifive_u: Correct UART0's IRQ in the device tree - 1 - 2019-03-19 Palmer Dabbelt New
[PULL,18/19] riscv: sifive_uart: Generate TX interrupt - 1 - 2019-03-19 Palmer Dabbelt New
[PULL,17/19] target/riscv: Remove unused struct - - - 2019-03-19 Palmer Dabbelt New
[PULL,16/19] riscv: sifive_u: Allow up to 4 CPUs to be created - - - 2019-03-19 Palmer Dabbelt New
[PULL,15/19] RISC-V: Update load reservation comment in do_interrupt - - - 2019-03-19 Palmer Dabbelt New
[PULL,14/19] RISC-V: Convert trap debugging to trace events - - - 2019-03-19 Palmer Dabbelt New
[PULL,13/19] RISC-V: Add support for vectored interrupts - - - 2019-03-19 Palmer Dabbelt New
[PULL,12/19] RISC-V: Change local interrupts from edge to level - - - 2019-03-19 Palmer Dabbelt New
[PULL,11/19] RISC-V: linux-user support for RVE ABI - - - 2019-03-19 Palmer Dabbelt New
[PULL,10/19] elf: Add RISC-V PSABI ELF header defines - 1 - 2019-03-19 Palmer Dabbelt New
[PULL,09/19] RISC-V: Remove unnecessary disassembler constraints - - - 2019-03-19 Palmer Dabbelt New
[PULL,08/19] RISC-V: Allow interrupt controllers to claim interrupts - - - 2019-03-19 Palmer Dabbelt New
[PULL,07/19] RISC-V: Replace __builtin_popcount with ctpop8 in PLIC - - - 2019-03-19 Palmer Dabbelt New
[PULL,06/19] riscv: pmp: Log pmp access errors as guest errors - - - 2019-03-19 Palmer Dabbelt New
[PULL,05/19] RISC-V: Add hooks to use the gdb xml files. - 1 - 2019-03-19 Palmer Dabbelt New
[PULL,04/19] RISC-V: Add debug support for accessing CSRs. - 1 - 2019-03-19 Palmer Dabbelt New
[PULL,03/19] RISC-V: Fixes to CSR_* register macros. - 1 - 2019-03-19 Palmer Dabbelt New
[PULL,02/19] RISC-V: Add 64-bit gdb xml files. - 1 - 2019-03-19 Palmer Dabbelt New
[PULL,01/19] RISC-V: Add 32-bit gdb xml files. - 1 - 2019-03-19 Palmer Dabbelt New
[PULL] target/riscv: Fix manually parsed 16 bit insn - 1 2 2019-03-18 Palmer Dabbelt New
[PULL,29/29] target/riscv: Remove decode_RV32_64G() - 1 - 2019-03-13 Palmer Dabbelt New
[PULL,28/29] target/riscv: Remove gen_system() - 1 - 2019-03-13 Palmer Dabbelt New
[PULL,27/29] target/riscv: Rename trans_arith to gen_arith - 1 - 2019-03-13 Palmer Dabbelt New
[PULL,26/29] target/riscv: Remove manual decoding of RV32/64M insn - 1 - 2019-03-13 Palmer Dabbelt New
[PULL,25/29] target/riscv: Remove shift and slt insn manual decoding - 1 - 2019-03-13 Palmer Dabbelt New
[PULL,24/29] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists - 1 - 2019-03-13 Palmer Dabbelt New
[PULL,23/29] target/riscv: Move gen_arith_imm() decoding into trans_* functions - 1 - 2019-03-13 Palmer Dabbelt New
[PULL,22/29] target/riscv: Remove manual decoding from gen_store() - 1 - 2019-03-13 Palmer Dabbelt New
[PULL,21/29] target/riscv: Remove manual decoding from gen_load() - 1 - 2019-03-13 Palmer Dabbelt New
[PULL,20/29] target/riscv: Remove manual decoding from gen_branch() - 1 - 2019-03-13 Palmer Dabbelt New
[PULL,19/29] target/riscv: Remove gen_jalr() 1 1 - 2019-03-13 Palmer Dabbelt New
[PULL,18/29] target/riscv: Convert quadrant 2 of RVXC insns to decodetree - 1 - 2019-03-13 Palmer Dabbelt New
[PULL,17/29] target/riscv: Convert quadrant 1 of RVXC insns to decodetree - 1 - 2019-03-13 Palmer Dabbelt New
[PULL,16/29] target/riscv: Convert quadrant 0 of RVXC insns to decodetree - 1 - 2019-03-13 Palmer Dabbelt New
[PULL,15/29] target/riscv: Convert RV priv insns to decodetree 1 1 - 2019-03-13 Palmer Dabbelt New
[PULL,14/29] target/riscv: Convert RV64D insns to decodetree 1 1 - 2019-03-13 Palmer Dabbelt New
[PULL,13/29] target/riscv: Convert RV32D insns to decodetree 1 1 - 2019-03-13 Palmer Dabbelt New
[PULL,12/29] target/riscv: Convert RV64F insns to decodetree 1 1 - 2019-03-13 Palmer Dabbelt New
[PULL,11/29] target/riscv: Convert RV32F insns to decodetree 1 1 - 2019-03-13 Palmer Dabbelt New
[PULL,10/29] target/riscv: Convert RV64A insns to decodetree 1 1 - 2019-03-13 Palmer Dabbelt New
[PULL,09/29] target/riscv: Convert RV32A insns to decodetree 1 1 - 2019-03-13 Palmer Dabbelt New
[PULL,08/29] target/riscv: Convert RVXM insns to decodetree 1 1 - 2019-03-13 Palmer Dabbelt New
[PULL,07/29] target/riscv: Convert RVXI csr insns to decodetree 1 1 - 2019-03-13 Palmer Dabbelt New
[PULL,06/29] target/riscv: Convert RVXI fence insns to decodetree 1 1 - 2019-03-13 Palmer Dabbelt New
[PULL,05/29] target/riscv: Convert RVXI arithmetic insns to decodetree 1 1 - 2019-03-13 Palmer Dabbelt New
[PULL,04/29] target/riscv: Convert RV64I load/store insns to decodetree 1 1 - 2019-03-13 Palmer Dabbelt New
[PULL,03/29] target/riscv: Convert RV32I load/store insns to decodetree 1 1 - 2019-03-13 Palmer Dabbelt New
[PULL,02/29] target/riscv: Convert RVXI branch insns to decodetree 1 2 - 2019-03-13 Palmer Dabbelt New
[PULL,01/29] target/riscv: Activate decodetree and implemnt LUI & AUIPC 1 1 - 2019-03-13 Palmer Dabbelt New
[PULL,29/29] target/riscv: Remove decode_RV32_64G() - 1 - 2019-03-12 Palmer Dabbelt New
[PULL,28/29] target/riscv: Remove gen_system() - 1 - 2019-03-12 Palmer Dabbelt New
[PULL,27/29] target/riscv: Rename trans_arith to gen_arith - 1 - 2019-03-12 Palmer Dabbelt New
[PULL,26/29] target/riscv: Remove manual decoding of RV32/64M insn - 1 - 2019-03-12 Palmer Dabbelt New
[PULL,25/29] target/riscv: Remove shift and slt insn manual decoding - 1 - 2019-03-12 Palmer Dabbelt New
[PULL,24/29] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists - 1 - 2019-03-12 Palmer Dabbelt New
[PULL,23/29] target/riscv: Move gen_arith_imm() decoding into trans_* functions - 1 - 2019-03-12 Palmer Dabbelt New
[PULL,22/29] target/riscv: Remove manual decoding from gen_store() - 1 - 2019-03-12 Palmer Dabbelt New
[PULL,21/29] target/riscv: Remove manual decoding from gen_load() - 1 - 2019-03-12 Palmer Dabbelt New
[PULL,20/29] target/riscv: Remove manual decoding from gen_branch() - 1 - 2019-03-12 Palmer Dabbelt New
[PULL,19/29] target/riscv: Remove gen_jalr() 1 1 - 2019-03-12 Palmer Dabbelt New
[PULL,18/29] target/riscv: Convert quadrant 2 of RVXC insns to decodetree - 1 - 2019-03-12 Palmer Dabbelt New
[PULL,17/29] target/riscv: Convert quadrant 1 of RVXC insns to decodetree - 1 - 2019-03-12 Palmer Dabbelt New
[PULL,16/29] target/riscv: Convert quadrant 0 of RVXC insns to decodetree - 1 - 2019-03-12 Palmer Dabbelt New
[PULL,15/29] target/riscv: Convert RV priv insns to decodetree 1 1 - 2019-03-12 Palmer Dabbelt New
[PULL,14/29] target/riscv: Convert RV64D insns to decodetree 1 1 - 2019-03-12 Palmer Dabbelt New
[PULL,13/29] target/riscv: Convert RV32D insns to decodetree 1 1 - 2019-03-12 Palmer Dabbelt New
[PULL,12/29] target/riscv: Convert RV64F insns to decodetree 1 1 - 2019-03-12 Palmer Dabbelt New
[PULL,11/29] target/riscv: Convert RV32F insns to decodetree 1 1 - 2019-03-12 Palmer Dabbelt New
[PULL,10/29] target/riscv: Convert RV64A insns to decodetree 1 1 - 2019-03-12 Palmer Dabbelt New
[PULL,09/29] target/riscv: Convert RV32A insns to decodetree 1 1 - 2019-03-12 Palmer Dabbelt New
[PULL,08/29] target/riscv: Convert RVXM insns to decodetree 1 1 - 2019-03-12 Palmer Dabbelt New
[PULL,07/29] target/riscv: Convert RVXI csr insns to decodetree 1 1 - 2019-03-12 Palmer Dabbelt New
[PULL,06/29] target/riscv: Convert RVXI fence insns to decodetree 1 1 - 2019-03-12 Palmer Dabbelt New
[PULL,05/29] target/riscv: Convert RVXI arithmetic insns to decodetree 1 1 - 2019-03-12 Palmer Dabbelt New
[PULL,04/29] target/riscv: Convert RV64I load/store insns to decodetree 1 1 - 2019-03-12 Palmer Dabbelt New
[PULL,03/29] target/riscv: Convert RV32I load/store insns to decodetree 1 1 - 2019-03-12 Palmer Dabbelt New
[PULL,02/29] target/riscv: Convert RVXI branch insns to decodetree 1 2 - 2019-03-12 Palmer Dabbelt New
[PULL,01/29] target/riscv: Activate decodetree and implemnt LUI & AUIPC 1 1 - 2019-03-12 Palmer Dabbelt New
[PULL,34/34] target/riscv: Remaining rvc insn reuse 32 bit translators - 1 - 2019-03-01 Palmer Dabbelt New
[PULL,33/34] target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64 - 1 - 2019-03-01 Palmer Dabbelt New
[PULL,32/34] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64 - 1 - 2019-03-01 Palmer Dabbelt New
[PULL,31/34] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns - 1 - 2019-03-01 Palmer Dabbelt New
[PULL,30/34] target/riscv: Convert @cs_2 insns to share translation functions - 1 - 2019-03-01 Palmer Dabbelt New
[PULL,29/34] target/riscv: Remove decode_RV32_64G() - 1 - 2019-03-01 Palmer Dabbelt New
[PULL,28/34] target/riscv: Remove gen_system() - 1 - 2019-03-01 Palmer Dabbelt New
[PULL,27/34] target/riscv: Rename trans_arith to gen_arith - 1 - 2019-03-01 Palmer Dabbelt New
[PULL,26/34] target/riscv: Remove manual decoding of RV32/64M insn - 1 - 2019-03-01 Palmer Dabbelt New
[PULL,25/34] target/riscv: Remove shift and slt insn manual decoding - 1 - 2019-03-01 Palmer Dabbelt New
[PULL,24/34] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists - 1 - 2019-03-01 Palmer Dabbelt New
[PULL,23/34] target/riscv: Move gen_arith_imm() decoding into trans_* functions - 1 - 2019-03-01 Palmer Dabbelt New
[PULL,22/34] target/riscv: Remove manual decoding from gen_store() - 1 - 2019-03-01 Palmer Dabbelt New
[PULL,21/34] target/riscv: Remove manual decoding from gen_load() - 1 - 2019-03-01 Palmer Dabbelt New
[PULL,20/34] target/riscv: Remove manual decoding from gen_branch() - 1 - 2019-03-01 Palmer Dabbelt New
[PULL,19/34] target/riscv: Remove gen_jalr() 1 1 - 2019-03-01 Palmer Dabbelt New
[PULL,18/34] target/riscv: Convert quadrant 2 of RVXC insns to decodetree - 1 - 2019-03-01 Palmer Dabbelt New
[PULL,17/34] target/riscv: Convert quadrant 1 of RVXC insns to decodetree - 1 - 2019-03-01 Palmer Dabbelt New
[PULL,16/34] target/riscv: Convert quadrant 0 of RVXC insns to decodetree - 1 - 2019-03-01 Palmer Dabbelt New
[PULL,15/34] target/riscv: Convert RV priv insns to decodetree 1 1 - 2019-03-01 Palmer Dabbelt New
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