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Patch A/R/T Date Submitter Delegate State
Regression for m68k causing Single-Step via GDB/RSP to not single step - - - 2019-05-26 Andrew Baumann via Qemu-devel New
The m68k gdbstub SR reg request doesnt include Condition-Codes - - - 2019-05-26 Andrew Baumann via Qemu-devel New
Incorrect Stack Pointer shadow register support on some m68k CPUs - - - 2019-05-26 Andrew Baumann via Qemu-devel New
[PULL,29/29] target/riscv: Only flush TLB if SATP.ASID changes - 1 - 2019-05-26 Palmer Dabbelt New
[PULL,28/29] target/riscv: More accurate handling of `sip` CSR - 1 - 2019-05-26 Palmer Dabbelt New
[PULL,27/29] target/riscv: Add checks for several RVC reserved operands - 1 - 2019-05-26 Palmer Dabbelt New
[PULL,26/29] target/riscv: Add the HGATP register masks - 1 - 2019-05-26 Palmer Dabbelt New
[PULL,25/29] target/riscv: Add the HSTATUS register masks - - - 2019-05-26 Palmer Dabbelt New
[PULL,24/29] target/riscv: Add Hypervisor CSR macros - 1 - 2019-05-26 Palmer Dabbelt New
[PULL,23/29] target/riscv: Allow setting mstatus virtulisation bits - - - 2019-05-26 Palmer Dabbelt New
[PULL,22/29] target/riscv: Add the MPV and MTL mstatus bits - 1 - 2019-05-26 Palmer Dabbelt New
[PULL,21/29] target/riscv: Improve the scause logic - 1 - 2019-05-26 Palmer Dabbelt New
[PULL,20/29] target/riscv: Trigger interrupt on MIP update asynchronously - 1 - 2019-05-26 Palmer Dabbelt New
[PULL,19/29] target/riscv: Mark privilege level 2 as reserved - 1 - 2019-05-26 Palmer Dabbelt New
[PULL,18/29] riscv: spike: Add a generic spike machine 1 1 - 2019-05-26 Palmer Dabbelt New
[PULL,17/29] target/riscv: Deprecate the generic no MMU CPUs - 1 - 2019-05-26 Palmer Dabbelt New
[PULL,16/29] target/riscv: Add a base 32 and 64 bit CPU - 1 - 2019-05-26 Palmer Dabbelt New
[PULL,15/29] target/riscv: Create settable CPU properties - 1 - 2019-05-26 Palmer Dabbelt New
[PULL,14/29] riscv: virt: Allow specifying a CPU via commandline - 1 - 2019-05-26 Palmer Dabbelt New
[PULL,13/29] linux-user/riscv: Add the CPU type as a comment - - - 2019-05-26 Palmer Dabbelt New
[PULL,12/29] target/riscv: Remove unused include of riscv_htif.h for virt board riscv - 2 - 2019-05-26 Palmer Dabbelt New
[PULL,11/29] target/riscv: Remove spaces from register names - 1 - 2019-05-26 Palmer Dabbelt New
[PULL,10/29] target/riscv: Split gen_arith_imm into functional and temp - 1 - 2019-05-26 Palmer Dabbelt New
[PULL,09/29] target/riscv: Split RVC32 and RVC64 insns into separate files - 1 - 2019-05-26 Palmer Dabbelt New
[PULL,08/29] target/riscv: Use pattern groups in insn16.decode - 1 - 2019-05-26 Palmer Dabbelt New
[PULL,07/29] target/riscv: Merge argument decode for RVC shifti - 1 - 2019-05-26 Palmer Dabbelt New
[PULL,06/29] target/riscv: Merge argument sets for insn32 and insn16 - 1 - 2019-05-26 Palmer Dabbelt New
[PULL,05/29] target/riscv: Use --static-decode for decodetree - 1 - 2019-05-26 Palmer Dabbelt New
[PULL,04/29] target/riscv: Name the argument sets for all of insn32 formats - 1 - 2019-05-26 Palmer Dabbelt New
[PULL,03/29] RISC-V: fix single stepping over ret and other branching instructions - 2 - 2019-05-26 Palmer Dabbelt New
[PULL,02/29] target/riscv: Do not allow sfence.vma from user mode - 2 - 2019-05-26 Palmer Dabbelt New
[PULL,01/29] SiFive RISC-V GPIO Device - 1 - 2019-05-26 Palmer Dabbelt New
[07/19] aspeed: add support for multiple NICs - - - 2019-05-26 Keno Fischer New
[v7,10/10] hw/m68k: define Macintosh Quadra 800 - - - 2019-05-25 Laurent Vivier New
[v7,09/10] hw/m68k: add a dummy SWIM floppy controller - 1 - 2019-05-25 Laurent Vivier New
[v7,08/10] hw/m68k: add Nubus support for macfb video card - 1 - 2019-05-25 Laurent Vivier New
[v7,07/10] hw/m68k: add Nubus support - 1 - 2019-05-25 Laurent Vivier New
[v7,06/10] hw/m68k: add macfb video card - 2 - 2019-05-25 Laurent Vivier New
[v7,05/10] hw/m68k: implement ADB bus support for via - 2 - 2019-05-25 Laurent Vivier New
[v7,04/10] hw/m68k: add via support - 1 - 2019-05-25 Laurent Vivier New
[v7,03/10] dp8393x: manage big endian bus - 2 1 2019-05-25 Laurent Vivier New
[v7,02/10] esp: add pseudo-DMA as used by Macintosh - - - 2019-05-25 Laurent Vivier New
[v7,01/10] escc: introduce a selector for the register bit - 1 - 2019-05-25 Laurent Vivier New
[19/19] aspeed/smc: Calculate checksum on normal DMA - - - 2019-05-25 Cédric Le Goater New
[18/19] aspeed/smc: inject errors in DMA checksum - - - 2019-05-25 Cédric Le Goater New
[17/19] aspeed/smc: add DMA calibration settings - - - 2019-05-25 Cédric Le Goater New
[16/19] aspeed/smc: add support for DMAs - - - 2019-05-25 Cédric Le Goater New
[15/19] aspeed: add a RAM memory region container - - - 2019-05-25 Cédric Le Goater New
[14/19] aspeed: remove the "ram" link - - - 2019-05-25 Cédric Le Goater New
[13/19] aspeed/smc: add a 'sdram_base' propertie - - - 2019-05-25 Cédric Le Goater New
[12/19] aspeed/timer: Ensure positive muldiv delta - - - 2019-05-25 Cédric Le Goater New
[11/19] aspeed/timer: Provide back-pressure information for short periods - - - 2019-05-25 Cédric Le Goater New
[10/19] aspeed/timer: Fix match calculations - - - 2019-05-25 Cédric Le Goater New
[09/19] aspeed/timer: Status register contains reload for stopped timer - - - 2019-05-25 Cédric Le Goater New
[08/19] aspeed/timer: Fix behaviour running Linux - - - 2019-05-25 Cédric Le Goater New
[07/19] aspeed: add support for multiple NICs - - - 2019-05-25 Cédric Le Goater New
[06/19] aspeed: introduce a configurable number of CPU per machine - - - 2019-05-25 Cédric Le Goater New
[05/19] hw/arm/aspeed: Add RTC to SoC - 1 - 2019-05-25 Cédric Le Goater New
[04/19] hw: timer: Add ASPEED RTC device - 1 - 2019-05-25 Cédric Le Goater New
[03/19] aspeed: add a per SoC mapping for the memory space - 2 - 2019-05-25 Cédric Le Goater New
[02/19] aspeed: add a per SoC mapping for the interrupt space - 2 - 2019-05-25 Cédric Le Goater New
[01/19] hw/arm/aspeed: Use object_initialize_child for correct ref. counting - 2 - 2019-05-25 Cédric Le Goater New
block/io_uring: use pkg-config for liburing - - - 2019-05-25 Stefan Hajnoczi New
migration: fix a typo - 1 - 2019-05-25 Li Qiang New
[2/2] Implement the PowerPC Floating Point Status and Control Register Fraction Rounded bit - - - 2019-05-25 Programmingkid New
[1/2] Implement Floating Point flag Fraction Rounded - - - 2019-05-25 Programmingkid New
[RFC,v1,23/23] target/riscv: Allow enabling the Hypervisor extension - - - 2019-05-24 Alistair Francis New
[RFC,v1,22/23] target/riscv: Call the second stage MMU in virtualisation mode - - - 2019-05-24 Alistair Francis New
[RFC,v1,21/23] target/riscv: Implement second stage MMU - - - 2019-05-24 Alistair Francis New
[RFC,v1,20/23] target/riscv: Allow specifying number of MMU stages - - - 2019-05-24 Alistair Francis New
[RFC,v1,19/23] target/riscv: Allow specifying MMU stage - - - 2019-05-24 Alistair Francis New
[RFC,v1,18/23] target/riscv: Add hfence instructions - - - 2019-05-24 Alistair Francis New
[RFC,v1,17/23] target/riscv: Add Hypervisor trap return support - - - 2019-05-24 Alistair Francis New
[RFC,v1,16/23] target/riscv: Add hypvervisor trap support - - - 2019-05-24 Alistair Francis New
[RFC,v1,15/23] riscv: plic: Always set sip.SEIP bit for HS - - - 2019-05-24 Alistair Francis New
[RFC,v1,14/23] riscv: plic: Remove unused interrupt functions - - - 2019-05-24 Alistair Francis New
[RFC,v1,13/23] target/riscv: Generate illegal instruction on WFI when V=1 - - - 2019-05-24 Alistair Francis New
[RFC,v1,12/23] target/ricsv: Flush the TLB on virtulisation mode changes - - - 2019-05-24 Alistair Francis New
[RFC,v1,11/23] target/riscv: Add background register swapping function - - - 2019-05-24 Alistair Francis New
[RFC,v1,10/23] target/riscv: Add background CSRs accesses - - - 2019-05-24 Alistair Francis New
[RFC,v1,09/23] target/riscv: Add Hypervisor CSR access functions - - - 2019-05-24 Alistair Francis New
[RFC,v1,08/23] target/riscv: Add support for background interrupt setting - - - 2019-05-24 Alistair Francis New
[RFC,v1,07/23] target/riscv: Remove strict perm checking for CSR R/W - - - 2019-05-24 Alistair Francis New
[RFC,v1,06/23] target/riscv: Dump Hypervisor registers if enabled - - - 2019-05-24 Alistair Francis New
[RFC,v1,05/23] target/riscv: Add the Hypervisor CSRs to CPUState - - - 2019-05-24 Alistair Francis New
[RFC,v1,04/23] target/riscv: Add the force HS exception mode - - - 2019-05-24 Alistair Francis New
[RFC,v1,03/23] target/riscv: Add the virtulisation mode - - - 2019-05-24 Alistair Francis New
[RFC,v1,02/23] target/riscv: Add the Hypervisor extension - - - 2019-05-24 Alistair Francis New
[RFC,v1,01/23] target/riscv: Don't set write permissions on dirty PTEs - - - 2019-05-24 Alistair Francis New
hw/s390x/ipl: Dubious use of qdev_reset_all_fn - - - 2019-05-24 David Hildenbrand New
Running linux on qemu omap - - - 2019-05-24 Aaro Koskinen New
[PULL,17/17] hw/intc/nvic: Use object_initialize_child for correct reference counting - 2 - 2019-05-24 Eduardo Habkost New
[PULL,16/17] hw/arm/mps2: Use object_initialize_child for correct reference counting - 1 - 2019-05-24 Eduardo Habkost New
[PULL,15/17] hw/microblaze/zynqmp: Use object_initialize_child for correct ref. counting - 2 - 2019-05-24 Eduardo Habkost New
[PULL,14/17] hw/microblaze/zynqmp: Use object_initialize_child for correct ref. counting - 2 - 2019-05-24 Eduardo Habkost New
[PULL,13/17] hw/microblaze/zynqmp: Let the SoC manage the IPI devices - 2 - 2019-05-24 Eduardo Habkost New
[PULL,12/17] hw/microblaze/zynqmp: Move the IPI state into the PMUSoC state - 2 - 2019-05-24 Eduardo Habkost New
[PULL,11/17] hw/mips: Use object_initialize_child for correct reference counting - 1 - 2019-05-24 Eduardo Habkost New
[PULL,10/17] hw/mips: Use object_initialize() on MIPSCPSState - 1 - 2019-05-24 Eduardo Habkost New
[PULL,09/17] hw/arm: Use object_initialize_child for correct reference counting - 2 - 2019-05-24 Eduardo Habkost New
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