Patchwork [PATCHv5,3/6] dt-bindings: PCI: Add NXP Layerscape SoCs PCIe Gen4 controller

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Submitter Zhiqiang Hou
Date April 12, 2019, 9:52 a.m.
Message ID <20190412095332.41370-4-Zhiqiang.Hou@nxp.com>
Download mbox | patch
Permalink /patch/771427/
State New
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Zhiqiang Hou - April 12, 2019, 9:52 a.m.
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>


Add PCIe Gen4 controller DT bindings of NXP Layerscape SoCs.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Reviewed-by: Rob Herring <robh@kernel.org>

---
V5:
 - Corrected the subject.

 .../bindings/pci/layerscape-pci-gen4.txt      | 52 +++++++++++++++++++
 MAINTAINERS                                   |  8 +++
 2 files changed, 60 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pci/layerscape-pci-gen4.txt

-- 
2.17.1

Patch

diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci-gen4.txt b/Documentation/devicetree/bindings/pci/layerscape-pci-gen4.txt

new file mode 100644
index 000000000000..b40fb5d15d3d

--- /dev/null

+++ b/Documentation/devicetree/bindings/pci/layerscape-pci-gen4.txt

@@ -0,0 +1,52 @@ 

+NXP Layerscape PCIe Gen4 controller

+

+This PCIe controller is based on the Mobiveil PCIe IP and thus inherits all

+the common properties defined in mobiveil-pcie.txt.

+

+Required properties:

+- compatible: should contain the platform identifier such as:

+  "fsl,lx2160a-pcie"

+- reg: base addresses and lengths of the PCIe controller register blocks.

+  "csr_axi_slave": Bridge config registers

+  "config_axi_slave": PCIe controller registers

+- interrupts: A list of interrupt outputs of the controller. Must contain an

+  entry for each entry in the interrupt-names property.

+- interrupt-names: It could include the following entries:

+  "intr": The interrupt that is asserted for controller interrupts

+  "aer": Asserted for aer interrupt when chip support the aer interrupt with

+	 none MSI/MSI-X/INTx mode,but there is interrupt line for aer.

+  "pme": Asserted for pme interrupt when chip support the pme interrupt with

+	 none MSI/MSI-X/INTx mode,but there is interrupt line for pme.

+- dma-coherent: Indicates that the hardware IP block can ensure the coherency

+  of the data transferred from/to the IP block. This can avoid the software

+  cache flush/invalid actions, and improve the performance significantly.

+- msi-parent : See the generic MSI binding described in

+  Documentation/devicetree/bindings/interrupt-controller/msi.txt.

+

+Example:

+

+	pcie@3400000 {

+		compatible = "fsl,lx2160a-pcie";

+		reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */

+		       0x80 0x00000000 0x0 0x00001000>; /* configuration space */

+		reg-names = "csr_axi_slave", "config_axi_slave";

+		interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */

+			     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */

+			     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */

+		interrupt-names = "aer", "pme", "intr";

+		#address-cells = <3>;

+		#size-cells = <2>;

+		device_type = "pci";

+		apio-wins = <8>;

+		ppio-wins = <8>;

+		dma-coherent;

+		bus-range = <0x0 0xff>;

+		msi-parent = <&its>;

+		ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>;

+		#interrupt-cells = <1>;

+		interrupt-map-mask = <0 0 0 7>;

+		interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,

+				<0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,

+				<0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,

+				<0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;

+	};

diff --git a/MAINTAINERS b/MAINTAINERS

index 1013e74b14f2..2d18c7213991 100644

--- a/MAINTAINERS

+++ b/MAINTAINERS

@@ -11835,6 +11835,14 @@  L:	linux-arm-kernel@lists.infradead.org

 S:	Maintained
 F:	drivers/pci/controller/dwc/*layerscape*
 
+PCI DRIVER FOR NXP LAYERSCAPE GEN4 CONTROLLER

+M:	Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

+L:	linux-pci@vger.kernel.org

+L:	linux-arm-kernel@lists.infradead.org

+S:	Maintained

+F:	Documentation/devicetree/bindings/pci/layerscape-pci-gen4.txt

+F:	drivers/pci/controller/mobibeil/pci-layerscape-gen4.c

+

 PCI DRIVER FOR GENERIC OF HOSTS
 M:	Will Deacon <will.deacon@arm.com>
 L:	linux-pci@vger.kernel.org