Patchwork [PATCHv5,19/20] PCI: mobiveil: Add 8-bit and 16-bit register accessors

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Submitter Zhiqiang Hou
Date April 12, 2019, 8:37 a.m.
Message ID <20190412083635.33626-20-Zhiqiang.Hou@nxp.com>
Download mbox | patch
Permalink /patch/771359/
State New
Headers show

Comments

Zhiqiang Hou - April 12, 2019, 8:37 a.m.
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>


There are some 8-bit and 16-bit registers in PCIe
configuration space, so add accessors for them.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>

Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>

---
V5:
 - Corrected and retouched the subject and changelog.
 - No functionality change.

 drivers/pci/controller/pcie-mobiveil.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

-- 
2.17.1

Patch

diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c

index 411e9779da12..456adfee393c 100644

--- a/drivers/pci/controller/pcie-mobiveil.c

+++ b/drivers/pci/controller/pcie-mobiveil.c

@@ -268,11 +268,31 @@  static u32 csr_readl(struct mobiveil_pcie *pcie, u32 off)

 	return csr_read(pcie, off, 0x4);
 }
 
+static u32 csr_readw(struct mobiveil_pcie *pcie, u32 off)

+{

+	return csr_read(pcie, off, 0x2);

+}

+

+static u32 csr_readb(struct mobiveil_pcie *pcie, u32 off)

+{

+	return csr_read(pcie, off, 0x1);

+}

+

 static void csr_writel(struct mobiveil_pcie *pcie, u32 val, u32 off)
 {
 	csr_write(pcie, val, off, 0x4);
 }
 
+static void csr_writew(struct mobiveil_pcie *pcie, u32 val, u32 off)

+{

+	csr_write(pcie, val, off, 0x2);

+}

+

+static void csr_writeb(struct mobiveil_pcie *pcie, u32 val, u32 off)

+{

+	csr_write(pcie, val, off, 0x1);

+}

+

 static bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie)
 {
 	return (csr_readl(pcie, LTSSM_STATUS) &