Patchwork [PATCHv5,11/20] PCI: mobiveil: Correct the fixup of Class Code field

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Submitter Zhiqiang Hou
Date April 12, 2019, 8:36 a.m.
Message ID <20190412083635.33626-12-Zhiqiang.Hou@nxp.com>
Download mbox | patch
Permalink /patch/771339/
State New
Headers show

Comments

Zhiqiang Hou - April 12, 2019, 8:36 a.m.
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>


Only fix up the Class Code field to PCI bridge, do not change the
Revision ID. And this patch also move the Class Code fixup to
function mobiveil_host_init().

Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver")
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>

Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>

---
V5:
 - Corrected and retouched the subject and changelog.

 drivers/pci/controller/pcie-mobiveil.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

-- 
2.17.1

Patch

diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c

index 78e575e71f4d..8eee1ab7ee24 100644

--- a/drivers/pci/controller/pcie-mobiveil.c

+++ b/drivers/pci/controller/pcie-mobiveil.c

@@ -653,6 +653,12 @@  static int mobiveil_host_init(struct mobiveil_pcie *pcie)

 				   type, resource_size(win->res));
 	}
 
+	/* fixup for PCIe class register */

+	value = csr_readl(pcie, PAB_INTP_AXI_PIO_CLASS);

+	value &= 0xff;

+	value |= (PCI_CLASS_BRIDGE_PCI << 16);

+	csr_writel(pcie, value, PAB_INTP_AXI_PIO_CLASS);

+

 	/* setup MSI hardware registers */
 	mobiveil_pcie_enable_msi(pcie);
 
@@ -896,9 +902,6 @@  static int mobiveil_pcie_probe(struct platform_device *pdev)

 		goto error;
 	}
 
-	/* fixup for PCIe class register */

-	csr_writel(pcie, 0x060402ab, PAB_INTP_AXI_PIO_CLASS);

-

 	/* initialize the IRQ domains */
 	ret = mobiveil_pcie_init_irq_domain(pcie);
 	if (ret) {