Patchwork [RFC,v1] PCI: qcom: Use quirk to override incorrect device class

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Submitter Marc Gonzalez
Date March 11, 2019, 2:56 p.m.
Message ID <94bb3f22-c5a7-1891-9d89-42a520e9a592@free.fr>
Download mbox | patch
Permalink /patch/746055/
State New
Headers show

Comments

Marc Gonzalez - March 11, 2019, 2:56 p.m.
Some chips report an incorrect device class. Override the incorrect
value using a quirk, instead of code in the read function.

Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr>
---
FWIW, this quirk is no longer required on recent chips:
msm8996 (tested by Stanimir), msm8998 (tested by me), sdm845 (untested) are unaffected
apq/ipq8064 is affected => what is the device ID for these chips?
others?

Stanimir added: "this will become a real problem (now we use the driver as RC)
when someone decide to use it as an endpoint"
---
 drivers/pci/controller/dwc/pcie-qcom.c | 14 ++++++--------
 1 file changed, 6 insertions(+), 8 deletions(-)
Stanimir Varbanov - March 12, 2019, 12:42 p.m.
Hi Marc,

Thanks for the patch!

On 3/11/19 4:56 PM, Marc Gonzalez wrote:
> Some chips report an incorrect device class. Override the incorrect
> value using a quirk, instead of code in the read function.
> 
> Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr>
> ---
> FWIW, this quirk is no longer required on recent chips:
> msm8996 (tested by Stanimir), msm8998 (tested by me), sdm845 (untested) are unaffected
> apq/ipq8064 is affected => what is the device ID for these chips?
> others?
> 
> Stanimir added: "this will become a real problem (now we use the driver as RC)
> when someone decide to use it as an endpoint"
> ---
>  drivers/pci/controller/dwc/pcie-qcom.c | 14 ++++++--------
>  1 file changed, 6 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index 3de5510fd3d5..94da2c9c2ad5 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -1136,17 +1136,15 @@ static int qcom_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
>  {
>  	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>  
> -	/* the device class is not reported correctly from the register */
> -	if (where == PCI_CLASS_REVISION && size == 4) {
> -		*val = readl(pci->dbi_base + PCI_CLASS_REVISION);
> -		*val &= 0xff;	/* keep revision id */
> -		*val |= PCI_CLASS_BRIDGE_PCI << 16;
> -		return PCIBIOS_SUCCESSFUL;
> -	}
> -

once you dropped the above snippet this function becomes absolutely
useless so please delete it at all and also from qcom_pcie_dw_ops.

>  	return dw_pcie_read(pci->dbi_base + where, size, val);
>  }
>  
> +static void qcom_fixup_class(struct pci_dev *dev)
> +{
> +	dev->class = PCI_CLASS_BRIDGE_PCI << 8;
> +}
> +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, PCI_ANY_ID, qcom_fixup_class);

I wonder, in case that dw_pcie_setup_rc() already has a write to
PCI_CLASS_DEVICE configuration register to set it as a bridge do we
still need to do the above fixup?
Marc Gonzalez - March 12, 2019, 5:18 p.m.
On 12/03/2019 13:42, Stanimir Varbanov wrote:

> On 3/11/19 4:56 PM, Marc Gonzalez wrote:
>
>> Some chips report an incorrect device class. Override the incorrect
>> value using a quirk, instead of code in the read function.
>>
>> Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr>
>> ---
>> FWIW, this quirk is no longer required on recent chips:
>> msm8996 (tested by Stanimir), msm8998 (tested by me), sdm845 (untested) are unaffected
>> apq/ipq8064 is affected => what is the device ID for these chips?
>> others?
>>
>> Stanimir added: "this will become a real problem (now we use the driver as RC)
>> when someone decide to use it as an endpoint"
>> ---
>>  drivers/pci/controller/dwc/pcie-qcom.c | 14 ++++++--------
>>  1 file changed, 6 insertions(+), 8 deletions(-)
>>
>> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
>> index 3de5510fd3d5..94da2c9c2ad5 100644
>> --- a/drivers/pci/controller/dwc/pcie-qcom.c
>> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
>> @@ -1136,17 +1136,15 @@ static int qcom_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
>>  {
>>  	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>>  
>> -	/* the device class is not reported correctly from the register */
>> -	if (where == PCI_CLASS_REVISION && size == 4) {
>> -		*val = readl(pci->dbi_base + PCI_CLASS_REVISION);
>> -		*val &= 0xff;	/* keep revision id */
>> -		*val |= PCI_CLASS_BRIDGE_PCI << 16;
>> -		return PCIBIOS_SUCCESSFUL;
>> -	}
>> -
> 
> once you dropped the above snippet this function becomes absolutely
> useless so please delete it at all and also from qcom_pcie_dw_ops.

Good catch.

>>  	return dw_pcie_read(pci->dbi_base + where, size, val);
>>  }
>>  
>> +static void qcom_fixup_class(struct pci_dev *dev)
>> +{
>> +	dev->class = PCI_CLASS_BRIDGE_PCI << 8;
>> +}
>> +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, PCI_ANY_ID, qcom_fixup_class);
> 
> I wonder, in case that dw_pcie_setup_rc() already has a write to
> PCI_CLASS_DEVICE configuration register to set it as a bridge do we
> still need to do the above fixup?

I don't know, I don't have an affected device. Unless the msm8998 /is/ affected,
and dw_pcie_setup_rc() actually fixes it?

Regards.
Marc Gonzalez - March 12, 2019, 5:34 p.m.
On 12/03/2019 18:18, Marc Gonzalez wrote:

> On 12/03/2019 13:42, Stanimir Varbanov wrote:
> 
>> I wonder, in case that dw_pcie_setup_rc() already has a write to
>> PCI_CLASS_DEVICE configuration register to set it as a bridge do we
>> still need to do the above fixup?
> 
> I don't know, I don't have an affected device. Unless the msm8998 /is/ affected,
> and dw_pcie_setup_rc() actually fixes it?

I think you hit the nail on the head...

If I comment out
//dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
from dw_pcie_setup_rc()
then pci_class() returns 0xff000000 instead of 0x6040000

So perhaps you're right: the quirk can be omitted altogether.
Unless it is not possible to program the device class on older chips?

Regards.

Patch

diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 3de5510fd3d5..94da2c9c2ad5 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -1136,17 +1136,15 @@  static int qcom_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
 {
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 
-	/* the device class is not reported correctly from the register */
-	if (where == PCI_CLASS_REVISION && size == 4) {
-		*val = readl(pci->dbi_base + PCI_CLASS_REVISION);
-		*val &= 0xff;	/* keep revision id */
-		*val |= PCI_CLASS_BRIDGE_PCI << 16;
-		return PCIBIOS_SUCCESSFUL;
-	}
-
 	return dw_pcie_read(pci->dbi_base + where, size, val);
 }
 
+static void qcom_fixup_class(struct pci_dev *dev)
+{
+	dev->class = PCI_CLASS_BRIDGE_PCI << 8;
+}
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, PCI_ANY_ID, qcom_fixup_class);
+
 static const struct dw_pcie_host_ops qcom_pcie_dw_ops = {
 	.host_init = qcom_pcie_host_init,
 	.rd_own_conf = qcom_pcie_rd_own_conf,