Patchwork [v2,3/3] clk: qcom: gcc-qcs404: Add cfg_offset for blsp1_uart3 clock

login
register
mail settings
Submitter Vinod Koul
Date Feb. 11, 2019, 7:39 a.m.
Message ID <20190211073928.20456-3-vkoul@kernel.org>
Download mbox | patch
Permalink /patch/722587/
State New
Headers show

Comments

Vinod Koul - Feb. 11, 2019, 7:39 a.m.
From: Taniya Das <tdas@codeaurora.org>

The CFG/M/N/D registers are at an offset of 0x20 from the CMD register
only for blsp1_uart3 clock, so add it for uart3 only.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Anu Ramanathan <anur@codeaurora.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
Changes in v2:
	Update changelog to indicate that uart3 alone suffers from this

 drivers/clk/qcom/gcc-qcs404.c | 1 +
 1 file changed, 1 insertion(+)
Stephen Boyd - Feb. 21, 2019, 10:18 p.m.
Quoting Vinod Koul (2019-02-10 23:39:28)
> From: Taniya Das <tdas@codeaurora.org>
> 
> The CFG/M/N/D registers are at an offset of 0x20 from the CMD register
> only for blsp1_uart3 clock, so add it for uart3 only.
> 
> Signed-off-by: Taniya Das <tdas@codeaurora.org>
> Signed-off-by: Anu Ramanathan <anur@codeaurora.org>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> ---

Applied to clk-next

Patch

diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c
index a7b2fe0fe505..5a62f64ada93 100644
--- a/drivers/clk/qcom/gcc-qcs404.c
+++ b/drivers/clk/qcom/gcc-qcs404.c
@@ -678,6 +678,7 @@  static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
 	.cmd_rcgr = 0x4014,
 	.mnd_width = 16,
 	.hid_width = 5,
+	.cfg_off = 0x20,
 	.parent_map = gcc_parent_map_0,
 	.freq_tbl = ftbl_blsp1_uart0_apps_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){