Patchwork [v1,1/2] PCI: ATS: Add function to check ATS page aligned request status.

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Submitter sathyanarayanan.kuppuswamy@linux.intel.com
Date Feb. 7, 2019, 6:41 p.m.
Message ID <91bfae8b1d4b424219e3ce3c1fc03559c73f1ae7.1549478584.git.sathyanarayanan.kuppuswamy@linux.intel.com>
Download mbox | patch
Permalink /patch/721057/
State New
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Comments

From: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>

Add a new function to return the status of ATS page aligned request
bit in ATS capability register. This function will be used by
drivers like IOMMU, if it is required to enforce page-aligned
requests in ATS.

Cc: Ashok Raj <ashok.raj@intel.com>
Cc: Jacob Pan <jacob.jun.pan@linux.intel.com>
Cc: Keith Busch <keith.busch@intel.com>
Suggested-by: Ashok Raj <ashok.raj@intel.com>
Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
---
 drivers/pci/ats.c             | 22 ++++++++++++++++++++++
 include/linux/pci.h           |  2 ++
 include/uapi/linux/pci_regs.h |  1 +
 3 files changed, 25 insertions(+)
Bjorn Helgaas - Feb. 7, 2019, 8:07 p.m.
Hi Kuppuswamy,

Previous changes to ats.c used subject lines starting with just
"PCI:".

I think it does make sense to include "ATS", but please do it in
the way we do it for other PCI features, e.g.,

  PCI/ATS: Add pci_ats_page_aligned() interface

On Thu, Feb 07, 2019 at 10:41:13AM -0800, sathyanarayanan.kuppuswamy@linux.intel.com wrote:
> From: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
> 
> Add a new function to return the status of ATS page aligned request
> bit in ATS capability register. This function will be used by
> drivers like IOMMU, if it is required to enforce page-aligned
> requests in ATS.

"return the Page Aligned Request bit in the ATS Capability Register"

This is just to make the terminology match the PCIe spec exactly so
it's easier to look up.

> Cc: Ashok Raj <ashok.raj@intel.com>
> Cc: Jacob Pan <jacob.jun.pan@linux.intel.com>
> Cc: Keith Busch <keith.busch@intel.com>
> Suggested-by: Ashok Raj <ashok.raj@intel.com>
> Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
> ---
>  drivers/pci/ats.c             | 22 ++++++++++++++++++++++
>  include/linux/pci.h           |  2 ++
>  include/uapi/linux/pci_regs.h |  1 +
>  3 files changed, 25 insertions(+)
> 
> diff --git a/drivers/pci/ats.c b/drivers/pci/ats.c
> index 5b78f3b1b918..7d14b9a1981e 100644
> --- a/drivers/pci/ats.c
> +++ b/drivers/pci/ats.c
> @@ -142,6 +142,28 @@ int pci_ats_queue_depth(struct pci_dev *dev)
>  }
>  EXPORT_SYMBOL_GPL(pci_ats_queue_depth);
>  
> +/**
> + * pci_ats_page_aligned - Return ATS page aligned request bit status.

Capitalize name of bit as above.

> + * @pdev: the PCI device
> + *
> + * Returns  value > 0 if address is aligned or 0 otherwise.

s/  / /

"if Untranslated Addresses generated by the device are always
aligned or ..."

> + *
> + * As per PCI spec, If page aligned request bit is set, it indicates
> + * the untranslated address is always aligned to a 4096 byte boundary.

"Per PCIe r4.0, sec 10.5.1.2, if the Page Aligned Request bit,
Untranslated Addresses generated by the device are always aligned to a
4096 byte boundary."

> + */
> +int pci_ats_page_aligned(struct pci_dev *pdev)
> +{
> +	u16 cap;
> +
> +	if (!pdev->ats_cap)
> +		return 0;
> +
> +	pci_read_config_word(pdev, pdev->ats_cap + PCI_ATS_CAP, &cap);
> +
> +	return PCI_ATS_CAP_PAGE_ALIGNED(cap);
> +}
> +EXPORT_SYMBOL_GPL(pci_ats_page_aligned);
> +
>  #ifdef CONFIG_PCI_PRI
>  /**
>   * pci_enable_pri - Enable PRI capability
> diff --git a/include/linux/pci.h b/include/linux/pci.h
> index 65f1d8c2f082..9724a8c0496b 100644
> --- a/include/linux/pci.h
> +++ b/include/linux/pci.h
> @@ -1524,11 +1524,13 @@ void pci_ats_init(struct pci_dev *dev);
>  int pci_enable_ats(struct pci_dev *dev, int ps);
>  void pci_disable_ats(struct pci_dev *dev);
>  int pci_ats_queue_depth(struct pci_dev *dev);
> +int pci_ats_page_aligned(struct pci_dev *dev);
>  #else
>  static inline void pci_ats_init(struct pci_dev *d) { }
>  static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; }
>  static inline void pci_disable_ats(struct pci_dev *d) { }
>  static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; }
> +static inline int pci_ats_page_aligned(struct pci_dev *dev) { return 0; }
>  #endif
>  
>  #ifdef CONFIG_PCIE_PTM
> diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
> index e1e9888c85e6..d42a759867b8 100644
> --- a/include/uapi/linux/pci_regs.h
> +++ b/include/uapi/linux/pci_regs.h
> @@ -866,6 +866,7 @@
>  #define PCI_ATS_CAP		0x04	/* ATS Capability Register */
>  #define  PCI_ATS_CAP_QDEP(x)	((x) & 0x1f)	/* Invalidate Queue Depth */
>  #define  PCI_ATS_MAX_QDEP	32	/* Max Invalidate Queue Depth */
> +#define  PCI_ATS_CAP_PAGE_ALIGNED(x)	0x0020 /* Page Aligned Request */

This is wrong because it *always* returns "true", regardless of the
value of the ATS Capability register.

I would prefer this:

  #define  PCI_ATS_CAP_PAGE_ALIGNED   0x0020

and then test it like this:

  if (cap & PCI_ATS_CAP_PAGE_ALIGNED)
    return 1;
  return 0;

>  #define PCI_ATS_CTRL		0x06	/* ATS Control Register */
>  #define  PCI_ATS_CTRL_ENABLE	0x8000	/* ATS Enable */
>  #define  PCI_ATS_CTRL_STU(x)	((x) & 0x1f)	/* Smallest Translation Unit */
> -- 
> 2.20.1
>
Sinan Kaya - Feb. 7, 2019, 8:38 p.m.
On 2/7/2019 1:41 PM, sathyanarayanan.kuppuswamy@linux.intel.com wrote:
> + * As per PCI spec, If page aligned request bit is set, it indicates
> + * the untranslated address is always aligned to a 4096 byte boundary.
> + */
> +int pci_ats_page_aligned(struct pci_dev *pdev)
> +{
> +	u16 cap;
> +
> +	if (!pdev->ats_cap)
> +		return 0;
> +
> +	pci_read_config_word(pdev, pdev->ats_cap + PCI_ATS_CAP, &cap);

If I remember this right, aligned request is only supported on ATS v1.1
but not supported on v1.0.

Can you please check the spec?
On 2/7/19 12:07 PM, Bjorn Helgaas wrote:
> Hi Kuppuswamy,
>
> Previous changes to ats.c used subject lines starting with just
> "PCI:".
>
> I think it does make sense to include "ATS", but please do it in
> the way we do it for other PCI features, e.g.,
>
>    PCI/ATS: Add pci_ats_page_aligned() interface
Got it. I will follow PCI/ATS format.
>
> On Thu, Feb 07, 2019 at 10:41:13AM -0800, sathyanarayanan.kuppuswamy@linux.intel.com wrote:
>> From: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
>>
>> Add a new function to return the status of ATS page aligned request
>> bit in ATS capability register. This function will be used by
>> drivers like IOMMU, if it is required to enforce page-aligned
>> requests in ATS.
> "return the Page Aligned Request bit in the ATS Capability Register"
>
> This is just to make the terminology match the PCIe spec exactly so
> it's easier to look up.
Will fix it in next version.
>
>> Cc: Ashok Raj <ashok.raj@intel.com>
>> Cc: Jacob Pan <jacob.jun.pan@linux.intel.com>
>> Cc: Keith Busch <keith.busch@intel.com>
>> Suggested-by: Ashok Raj <ashok.raj@intel.com>
>> Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
>> ---
>>   drivers/pci/ats.c             | 22 ++++++++++++++++++++++
>>   include/linux/pci.h           |  2 ++
>>   include/uapi/linux/pci_regs.h |  1 +
>>   3 files changed, 25 insertions(+)
>>
>> diff --git a/drivers/pci/ats.c b/drivers/pci/ats.c
>> index 5b78f3b1b918..7d14b9a1981e 100644
>> --- a/drivers/pci/ats.c
>> +++ b/drivers/pci/ats.c
>> @@ -142,6 +142,28 @@ int pci_ats_queue_depth(struct pci_dev *dev)
>>   }
>>   EXPORT_SYMBOL_GPL(pci_ats_queue_depth);
>>   
>> +/**
>> + * pci_ats_page_aligned - Return ATS page aligned request bit status.
> Capitalize name of bit as above.
Agreed.
>
>> + * @pdev: the PCI device
>> + *
>> + * Returns  value > 0 if address is aligned or 0 otherwise.
> s/  / /
>
> "if Untranslated Addresses generated by the device are always
> aligned or ..."
>
>> + *
>> + * As per PCI spec, If page aligned request bit is set, it indicates
>> + * the untranslated address is always aligned to a 4096 byte boundary.
> "Per PCIe r4.0, sec 10.5.1.2, if the Page Aligned Request bit,
> Untranslated Addresses generated by the device are always aligned to a
> 4096 byte boundary."
>
>> + */
>> +int pci_ats_page_aligned(struct pci_dev *pdev)
>> +{
>> +	u16 cap;
>> +
>> +	if (!pdev->ats_cap)
>> +		return 0;
>> +
>> +	pci_read_config_word(pdev, pdev->ats_cap + PCI_ATS_CAP, &cap);
>> +
>> +	return PCI_ATS_CAP_PAGE_ALIGNED(cap);
>> +}
>> +EXPORT_SYMBOL_GPL(pci_ats_page_aligned);
>> +
>>   #ifdef CONFIG_PCI_PRI
>>   /**
>>    * pci_enable_pri - Enable PRI capability
>> diff --git a/include/linux/pci.h b/include/linux/pci.h
>> index 65f1d8c2f082..9724a8c0496b 100644
>> --- a/include/linux/pci.h
>> +++ b/include/linux/pci.h
>> @@ -1524,11 +1524,13 @@ void pci_ats_init(struct pci_dev *dev);
>>   int pci_enable_ats(struct pci_dev *dev, int ps);
>>   void pci_disable_ats(struct pci_dev *dev);
>>   int pci_ats_queue_depth(struct pci_dev *dev);
>> +int pci_ats_page_aligned(struct pci_dev *dev);
>>   #else
>>   static inline void pci_ats_init(struct pci_dev *d) { }
>>   static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; }
>>   static inline void pci_disable_ats(struct pci_dev *d) { }
>>   static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; }
>> +static inline int pci_ats_page_aligned(struct pci_dev *dev) { return 0; }
>>   #endif
>>   
>>   #ifdef CONFIG_PCIE_PTM
>> diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
>> index e1e9888c85e6..d42a759867b8 100644
>> --- a/include/uapi/linux/pci_regs.h
>> +++ b/include/uapi/linux/pci_regs.h
>> @@ -866,6 +866,7 @@
>>   #define PCI_ATS_CAP		0x04	/* ATS Capability Register */
>>   #define  PCI_ATS_CAP_QDEP(x)	((x) & 0x1f)	/* Invalidate Queue Depth */
>>   #define  PCI_ATS_MAX_QDEP	32	/* Max Invalidate Queue Depth */
>> +#define  PCI_ATS_CAP_PAGE_ALIGNED(x)	0x0020 /* Page Aligned Request */
> This is wrong because it *always* returns "true", regardless of the
> value of the ATS Capability register.
>
> I would prefer this:
>
>    #define  PCI_ATS_CAP_PAGE_ALIGNED   0x0020
Good catch. it looks like I messed it when I did some cleanup. Sorry 
about it. Initially it was (x & 0x0020).
>
> and then test it like this:
>
>    if (cap & PCI_ATS_CAP_PAGE_ALIGNED)
>      return 1;
>    return 0;
Ok.
>>   #define PCI_ATS_CTRL		0x06	/* ATS Control Register */
>>   #define  PCI_ATS_CTRL_ENABLE	0x8000	/* ATS Enable */
>>   #define  PCI_ATS_CTRL_STU(x)	((x) & 0x1f)	/* Smallest Translation Unit */
>> -- 
>> 2.20.1
>>
On 2/7/19 12:38 PM, Sinan Kaya wrote:
>
> On 2/7/2019 1:41 PM, sathyanarayanan.kuppuswamy@linux.intel.com wrote:
>> + * As per PCI spec, If page aligned request bit is set, it indicates
>> + * the untranslated address is always aligned to a 4096 byte boundary.
>> + */
>> +int pci_ats_page_aligned(struct pci_dev *pdev)
>> +{
>> +    u16 cap;
>> +
>> +    if (!pdev->ats_cap)
>> +        return 0;
>> +
>> +    pci_read_config_word(pdev, pdev->ats_cap + PCI_ATS_CAP, &cap);
>
> If I remember this right, aligned request is only supported on ATS v1.1
> but not supported on v1.0.
Its added in v1.1.
>
> Can you please check the spec?
>
Sinan Kaya - Feb. 8, 2019, 1:58 a.m.
On 2/7/2019 5:16 PM, sathyanarayanan kuppuswamy wrote:
>> If I remember this right, aligned request is only supported on ATS v1.1
>> but not supported on v1.0.
> Its added in v1.1.

This means that you should probably have some kind of version check
here.
On 2/7/19 5:58 PM, Sinan Kaya wrote:
>
> On 2/7/2019 5:16 PM, sathyanarayanan kuppuswamy wrote:
>>> If I remember this right, aligned request is only supported on ATS v1.1
>>> but not supported on v1.0.
>> Its added in v1.1.
>
> This means that you should probably have some kind of version check
> here.

There is no version field in ATS v1.0 spec. Also, If I follow the 
history log in PCI spec, I think ATS if first added at v1.2. Please 
correct me if I am wrong.
Sinan Kaya - Feb. 9, 2019, 4:49 a.m.
On 2/8/2019 8:02 PM, sathyanarayanan kuppuswamy wrote:
>> This means that you should probably have some kind of version check
>> here.
> 
> There is no version field in ATS v1.0 spec. Also, If I follow the 
> history log in PCI spec, I think ATS if first added at v1.2. Please 
> correct me if I am wrong.

v1.2 was incorporated into PCIe spec at that time. However, the ATS spec
is old and there could be some HW that could claim to be ATS compatible.
I know AMD GPUs declare ATS capability.

See this ECN

https://composter.com.ua/documents/ats_r1.1_26Jan09.pdf

You need to validate the version field from ATS capability header to be
1 before reading this register.

See Table 5-1:  ATS Extended Capability Header
Raj, Ashok - Feb. 11, 2019, 7:15 p.m.
On Fri, Feb 08, 2019 at 11:49:55PM -0500, Sinan Kaya wrote:
> On 2/8/2019 8:02 PM, sathyanarayanan kuppuswamy wrote:
> >>This means that you should probably have some kind of version check
> >>here.
> >
> >There is no version field in ATS v1.0 spec. Also, If I follow the history
> >log in PCI spec, I think ATS if first added at v1.2. Please correct me if
> >I am wrong.
> 
> v1.2 was incorporated into PCIe spec at that time. However, the ATS spec
> is old and there could be some HW that could claim to be ATS compatible.
> I know AMD GPUs declare ATS capability.

It seems rather odd we have to check for ATS version.

I always assumed unspecified bits (Reserved) must be 0. We only check
this if ATS is enabled, and this particular bit wasn't given away for another
feature.

Is it really required to check for ATS version before consuming this?


> 
> See this ECN
> 
> https://composter.com.ua/documents/ats_r1.1_26Jan09.pdf
> 
> You need to validate the version field from ATS capability header to be
> 1 before reading this register.
> 
> See Table 5-1:  ATS Extended Capability Header
On 2/11/19 11:15 AM, Raj, Ashok wrote:
> On Fri, Feb 08, 2019 at 11:49:55PM -0500, Sinan Kaya wrote:
>> On 2/8/2019 8:02 PM, sathyanarayanan kuppuswamy wrote:
>>>> This means that you should probably have some kind of version check
>>>> here.
>>> There is no version field in ATS v1.0 spec. Also, If I follow the history
>>> log in PCI spec, I think ATS if first added at v1.2. Please correct me if
>>> I am wrong.
>> v1.2 was incorporated into PCIe spec at that time. However, the ATS spec
>> is old and there could be some HW that could claim to be ATS compatible.
>> I know AMD GPUs declare ATS capability.
> It seems rather odd we have to check for ATS version.
>
> I always assumed unspecified bits (Reserved) must be 0. We only check
> this if ATS is enabled, and this particular bit wasn't given away for another
> feature.
>
> Is it really required to check for ATS version before consuming this?
If the version check is required then, it needs to be added before 
reading "Invalidate Queue Depth" value as well.
>
>
>> See this ECN
>>
>> https://composter.com.ua/documents/ats_r1.1_26Jan09.pdf
>>
>> You need to validate the version field from ATS capability header to be
>> 1 before reading this register.
>>
>> See Table 5-1:  ATS Extended Capability Header
Sinan Kaya - Feb. 11, 2019, 8:35 p.m.
On 2/11/2019 2:15 PM, Raj, Ashok wrote:
> It seems rather odd we have to check for ATS version.
> 
> I always assumed unspecified bits (Reserved) must be 0. We only check
> this if ATS is enabled, and this particular bit wasn't given away for another
> feature.
> 
> Is it really required to check for ATS version before consuming this?

Reading again, it looks like version check is not necessary since it
is implied by the presence of this bit per this paragraph.

Page Aligned Request – If Set, indicates the Untranslated Address is 
always aligned to a 4096 byte boundary.  Setting this bit is 
recommended.  This bit permits software to distinguish between 
implementations compatible with earlier version of this specification 
that permitted a requester to supply anything in bits [11:2].

Patch

diff --git a/drivers/pci/ats.c b/drivers/pci/ats.c
index 5b78f3b1b918..7d14b9a1981e 100644
--- a/drivers/pci/ats.c
+++ b/drivers/pci/ats.c
@@ -142,6 +142,28 @@  int pci_ats_queue_depth(struct pci_dev *dev)
 }
 EXPORT_SYMBOL_GPL(pci_ats_queue_depth);
 
+/**
+ * pci_ats_page_aligned - Return ATS page aligned request bit status.
+ * @pdev: the PCI device
+ *
+ * Returns  value > 0 if address is aligned or 0 otherwise.
+ *
+ * As per PCI spec, If page aligned request bit is set, it indicates
+ * the untranslated address is always aligned to a 4096 byte boundary.
+ */
+int pci_ats_page_aligned(struct pci_dev *pdev)
+{
+	u16 cap;
+
+	if (!pdev->ats_cap)
+		return 0;
+
+	pci_read_config_word(pdev, pdev->ats_cap + PCI_ATS_CAP, &cap);
+
+	return PCI_ATS_CAP_PAGE_ALIGNED(cap);
+}
+EXPORT_SYMBOL_GPL(pci_ats_page_aligned);
+
 #ifdef CONFIG_PCI_PRI
 /**
  * pci_enable_pri - Enable PRI capability
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 65f1d8c2f082..9724a8c0496b 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -1524,11 +1524,13 @@  void pci_ats_init(struct pci_dev *dev);
 int pci_enable_ats(struct pci_dev *dev, int ps);
 void pci_disable_ats(struct pci_dev *dev);
 int pci_ats_queue_depth(struct pci_dev *dev);
+int pci_ats_page_aligned(struct pci_dev *dev);
 #else
 static inline void pci_ats_init(struct pci_dev *d) { }
 static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; }
 static inline void pci_disable_ats(struct pci_dev *d) { }
 static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; }
+static inline int pci_ats_page_aligned(struct pci_dev *dev) { return 0; }
 #endif
 
 #ifdef CONFIG_PCIE_PTM
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index e1e9888c85e6..d42a759867b8 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -866,6 +866,7 @@ 
 #define PCI_ATS_CAP		0x04	/* ATS Capability Register */
 #define  PCI_ATS_CAP_QDEP(x)	((x) & 0x1f)	/* Invalidate Queue Depth */
 #define  PCI_ATS_MAX_QDEP	32	/* Max Invalidate Queue Depth */
+#define  PCI_ATS_CAP_PAGE_ALIGNED(x)	0x0020 /* Page Aligned Request */
 #define PCI_ATS_CTRL		0x06	/* ATS Control Register */
 #define  PCI_ATS_CTRL_ENABLE	0x8000	/* ATS Enable */
 #define  PCI_ATS_CTRL_STU(x)	((x) & 0x1f)	/* Smallest Translation Unit */