Patchwork [v1,4/8] arm64: dts: msm8996: Add UFS PHY reset controller

login
register
mail settings
Submitter Evan Green
Date Jan. 11, 2019, 11:01 p.m.
Message ID <20190111230129.127037-5-evgreen@chromium.org>
Download mbox | patch
Permalink /patch/698135/
State New
Headers show

Comments

Evan Green - Jan. 11, 2019, 11:01 p.m.
Add the reset controller for the UFS controller, and wire it up
so that the UFS PHY can initialize itself without relying on
implicit sequencing between the two drivers.

Signed-off-by: Evan Green <evgreen@chromium.org>
---

 arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)
Stephen Boyd - Jan. 18, 2019, 10:20 p.m.
Quoting Evan Green (2019-01-11 15:01:25)
> Add the reset controller for the UFS controller, and wire it up
> so that the UFS PHY can initialize itself without relying on
> implicit sequencing between the two drivers.
> 
> Signed-off-by: Evan Green <evgreen@chromium.org>
> ---

Reviewed-by: Stephen Boyd <swboyd@chromium.org>

Patch

diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 99b7495455a62..179f1988d45c5 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -663,10 +663,11 @@ 
 			clock-names = "ref_clk_src", "ref_clk";
 			clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
 				 <&gcc GCC_UFS_CLKREF_CLK>;
+			resets = <&ufshc 0>;
 			status = "disabled";
 		};
 
-		ufshc@624000 {
+		ufshc: ufshc@624000 {
 			compatible = "qcom,ufshc";
 			reg = <0x624000 0x2500>;
 			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
@@ -722,6 +723,7 @@ 
 				<0 0>;
 
 			lanes-per-direction = <1>;
+			#reset-cells = <1>;
 			status = "disabled";
 
 			ufs_variant {