Patchwork [15/22] x86/entry: Add TIF_NEED_FPU_LOAD

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Submitter Sebastian Andrzej Siewior
Date Jan. 9, 2019, 11:47 a.m.
Message ID <20190109114744.10936-16-bigeasy@linutronix.de>
Download mbox | patch
Permalink /patch/695743/
State New
Headers show

Comments

Sebastian Andrzej Siewior - Jan. 9, 2019, 11:47 a.m.
Add TIF_NEED_FPU_LOAD. This is reserved for loading the FPU registers
before returning to userland. This flag must not be set for systems
without a FPU.
If this flag is cleared, the CPU's FPU register hold the current content
of current()'s FPU register. The in-memory copy (union fpregs_state) is
not valid.
If this flag is set, then all of CPU's FPU register may hold a random
value (except for PKRU) and it is required to load the content of the
FPU register on return to userland.

It is introduced now, so we can add code handling it now before adding
the main feature.

Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
---
 arch/x86/include/asm/thread_info.h | 2 ++
 1 file changed, 2 insertions(+)
Borislav Petkov - Jan. 30, 2019, 11:55 a.m.
On Wed, Jan 09, 2019 at 12:47:37PM +0100, Sebastian Andrzej Siewior wrote:
> Add TIF_NEED_FPU_LOAD. This is reserved for loading the FPU registers
> before returning to userland. This flag must not be set for systems
> without a FPU.
> If this flag is cleared, the CPU's FPU register hold the current content
> of current()'s FPU register. The in-memory copy (union fpregs_state) is
> not valid.
> If this flag is set, then all of CPU's FPU register may hold a random
> value (except for PKRU) and it is required to load the content of the
> FPU register on return to userland.

This definitely needs to be written somewhere in

arch/x86/include/asm/fpu/internal.h

or where we decide to put the FPU handling rules.

Patch

diff --git a/arch/x86/include/asm/thread_info.h b/arch/x86/include/asm/thread_info.h
index e0eccbcb8447d..f9453536f9bbc 100644
--- a/arch/x86/include/asm/thread_info.h
+++ b/arch/x86/include/asm/thread_info.h
@@ -88,6 +88,7 @@  struct thread_info {
 #define TIF_USER_RETURN_NOTIFY	11	/* notify kernel of userspace return */
 #define TIF_UPROBE		12	/* breakpointed or singlestepping */
 #define TIF_PATCH_PENDING	13	/* pending live patching update */
+#define TIF_NEED_FPU_LOAD	14	/* load FPU on return to userspace */
 #define TIF_NOCPUID		15	/* CPUID is not accessible in userland */
 #define TIF_NOTSC		16	/* TSC is not accessible in userland */
 #define TIF_IA32		17	/* IA32 compatibility process */
@@ -117,6 +118,7 @@  struct thread_info {
 #define _TIF_USER_RETURN_NOTIFY	(1 << TIF_USER_RETURN_NOTIFY)
 #define _TIF_UPROBE		(1 << TIF_UPROBE)
 #define _TIF_PATCH_PENDING	(1 << TIF_PATCH_PENDING)
+#define _TIF_NEED_FPU_LOAD	(1 << TIF_NEED_FPU_LOAD)
 #define _TIF_NOCPUID		(1 << TIF_NOCPUID)
 #define _TIF_NOTSC		(1 << TIF_NOTSC)
 #define _TIF_IA32		(1 << TIF_IA32)