Patchwork [v2,5/5] net: dsa: qca8k: disable delay for RGMII mode

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Submitter Vinod Koul
Date Jan. 8, 2019, 4:29 p.m.
Message ID <20190108162926.17806-6-vkoul@kernel.org>
Download mbox | patch
Permalink /patch/695009/
State New
Headers show

Comments

Vinod Koul - Jan. 8, 2019, 4:29 p.m.
In RGMII mode we should not have any delay in phy, so disable
the delay.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
 drivers/net/dsa/qca8k.c | 16 ++++------------
 1 file changed, 4 insertions(+), 12 deletions(-)
Florian Fainelli - Jan. 8, 2019, 6 p.m.
On 1/8/19 8:29 AM, Vinod Koul wrote:
> In RGMII mode we should not have any delay in phy, so disable
> the delay.

This seems to apply to the port's MAC itself, so the commit message
should be mentioning the port's MAC not the PHY, right?

> 
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> ---
>  drivers/net/dsa/qca8k.c | 16 ++++------------
>  1 file changed, 4 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c
> index 7e97e620bd44..a4b6cda38016 100644
> --- a/drivers/net/dsa/qca8k.c
> +++ b/drivers/net/dsa/qca8k.c
> @@ -420,7 +420,7 @@ qca8k_mib_init(struct qca8k_priv *priv)
>  static int
>  qca8k_set_pad_ctrl(struct qca8k_priv *priv, int port, int mode)
>  {
> -	u32 reg;
> +	u32 reg, val;
>  
>  	switch (port) {
>  	case 0:
> @@ -439,17 +439,9 @@ qca8k_set_pad_ctrl(struct qca8k_priv *priv, int port, int mode)
>  	 */
>  	switch (mode) {
>  	case PHY_INTERFACE_MODE_RGMII:
> -		qca8k_write(priv, reg,
> -			    QCA8K_PORT_PAD_RGMII_EN |
> -			    QCA8K_PORT_PAD_RGMII_TX_DELAY(3) |
> -			    QCA8K_PORT_PAD_RGMII_RX_DELAY(3));
> -
> -		/* According to the datasheet, RGMII delay is enabled through
> -		 * PORT5_PAD_CTRL for all ports, rather than individual port
> -		 * registers
> -		 */
> -		qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL,
> -			    QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);
> +		/* RGMII mode means no delay so don't enable the delay */
> +		val = QCA8K_PORT_PAD_RGMII_EN;
> +		qca8k_write(priv, reg, val);
>  		break;
>  	case PHY_INTERFACE_MODE_SGMII:
>  		qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN);
>
Vinod Koul - Jan. 9, 2019, 4:43 a.m.
Hi Florian,

On 08-01-19, 10:00, Florian Fainelli wrote:
> On 1/8/19 8:29 AM, Vinod Koul wrote:
> > In RGMII mode we should not have any delay in phy, so disable
> > the delay.
> 
> This seems to apply to the port's MAC itself, so the commit message
> should be mentioning the port's MAC not the PHY, right?

Yes will update

Patch

diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c
index 7e97e620bd44..a4b6cda38016 100644
--- a/drivers/net/dsa/qca8k.c
+++ b/drivers/net/dsa/qca8k.c
@@ -420,7 +420,7 @@  qca8k_mib_init(struct qca8k_priv *priv)
 static int
 qca8k_set_pad_ctrl(struct qca8k_priv *priv, int port, int mode)
 {
-	u32 reg;
+	u32 reg, val;
 
 	switch (port) {
 	case 0:
@@ -439,17 +439,9 @@  qca8k_set_pad_ctrl(struct qca8k_priv *priv, int port, int mode)
 	 */
 	switch (mode) {
 	case PHY_INTERFACE_MODE_RGMII:
-		qca8k_write(priv, reg,
-			    QCA8K_PORT_PAD_RGMII_EN |
-			    QCA8K_PORT_PAD_RGMII_TX_DELAY(3) |
-			    QCA8K_PORT_PAD_RGMII_RX_DELAY(3));
-
-		/* According to the datasheet, RGMII delay is enabled through
-		 * PORT5_PAD_CTRL for all ports, rather than individual port
-		 * registers
-		 */
-		qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL,
-			    QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);
+		/* RGMII mode means no delay so don't enable the delay */
+		val = QCA8K_PORT_PAD_RGMII_EN;
+		qca8k_write(priv, reg, val);
 		break;
 	case PHY_INTERFACE_MODE_SGMII:
 		qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN);