Patchwork Regression with commit PCI: mvebu: Convert to PCI emulated bridge config space

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Submitter Thomas Petazzoni
Date Jan. 8, 2019, 10:48 a.m.
Message ID <20190108114817.2bb15d5e@windsurf>
Download mbox | patch
Permalink /patch/694669/
State New
Headers show

Comments

Thomas Petazzoni - Jan. 8, 2019, 10:48 a.m.
Hello Luis,

Sorry for the long delay, the Christmas/New Year vacation and some
personal issues got in the way.

On Tue, 18 Dec 2018 23:13:59 +0000, Luís Mendes wrote:

> The complete lspci outputs follow in attachments.
> 
> In the working case, region 5, is at e0200000 with size 256k and is
> immediately followed by the expansion rom at  e0240000 [disabled]
> [size=128K], however in the non-working case,
> region 5 has a completely different address, and regions are not contiguous.
> Another difference is at:
> Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit+
>         Address: 00000000f1020a04  Data: 0f12
> 
> vs
> 
>     Capabilities: [a0] MSI: Enable- Count=1/1 Maskable- 64bit+
>         Address: 0000000000000000  Data: 0000
> 
> So it looks like MSI is not being enabled with the new PCI management
> code and looks like the PCI rom maybe mapped to an invalid memory
> address, causing the ioremap to fail.

Could you apply the patches attached (one is meant to be used with 4.20
as-is, and the other meant to be used with 4.20 +
1f08673eef1236f7d02d93fcf596bb8531ef0d12 reverted), and post the
complete boot logs ?

You will most likely have to increase CONFIG_LOG_BUF_SHIFT to avoid
having dropped messages, as my additional debug messages are quite
verbose. I'm using CONFIG_LOG_BUF_SHIFT=16.

Having these boot lots will help me investigate the issue.

Best regards,

Thomas
Thomas Petazzoni - Jan. 9, 2019, 8:15 a.m.
Hello Luis,

On Tue, 8 Jan 2019 23:22:05 +0000, Luís Mendes wrote:

> > Sorry for the long delay, the Christmas/New Year vacation and some
> > personal issues got in the way.  
> No problem, life has its priorities! and by the way: Happy new year!

Thanks, you too!


> > You will most likely have to increase CONFIG_LOG_BUF_SHIFT to avoid
> > having dropped messages, as my additional debug messages are quite
> > verbose. I'm using CONFIG_LOG_BUF_SHIFT=16.  
> The logs from the new kernel are not starting at 0.0 sec, as
> CONFIG_LOG_BUF_SHIFT=16 wasn't large enough, but for the reverted
> patch case I changed to CONFIG_LOG_BUF_SHIFT=17.
> If you find relevant information can be missing tell me and I will
> recompile the kernel with the patch
> 1f08673eef1236f7d02d93fcf596bb8531ef0d12 applied and
> CONFIG_LOG_BUF_SHIFT=17. I believe it won't be needed though, since
> the pci logs are practically complete.

Sadly, the kern_4.20_debug.log file is incomplete. I would like to at
least see it starting from:

Jan  8 22:57:51 picolo kernel: [    6.792819] mvebu-pcie soc:pcie: MEM: [mem 0xd0000000-0xefffffff], IO: [io  0xffe00000-0xffefffff]

(this line from the reverted log, but I'd like to see it in the non-reverted log as well)

Thanks!

Thomas

Patch

From ac0aa231c23390150dddfdf923400af2a4a4e86b Mon Sep 17 00:00:00 2001
From: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Date: Tue, 8 Jan 2019 10:59:19 +0100
Subject: [PATCH] PCI: mvebu: add debug

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
---
 drivers/pci/controller/pci-mvebu.c | 17 ++++++++++++++---
 1 file changed, 14 insertions(+), 3 deletions(-)

diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c
index dacad51f19e7..94aa7e42c5e2 100644
--- a/drivers/pci/controller/pci-mvebu.c
+++ b/drivers/pci/controller/pci-mvebu.c
@@ -796,8 +796,12 @@  static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
 		return PCIBIOS_DEVICE_NOT_FOUND;
 
 	/* Access the emulated PCI-to-PCI bridge */
-	if (bus->number == 0)
+	if (bus->number == 0) {
+		dev_info(&pcie->pdev->dev,
+			 "%s: devfn=0x%x, where=0x%x, size=%d, val=0x%x\n",
+			 __func__, devfn, where, size, val);
 		return mvebu_sw_pci_bridge_write(port, where, size, val);
+	}
 
 	if (!mvebu_pcie_link_up(port))
 		return PCIBIOS_DEVICE_NOT_FOUND;
@@ -824,8 +828,13 @@  static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
 	}
 
 	/* Access the emulated PCI-to-PCI bridge */
-	if (bus->number == 0)
-		return mvebu_sw_pci_bridge_read(port, where, size, val);
+	if (bus->number == 0) {
+		ret = mvebu_sw_pci_bridge_read(port, where, size, val);
+		dev_info(&pcie->pdev->dev,
+			 "%s: devfn=0x%x, where=0x%x, size=%d, val=0x%x\n",
+			 __func__, devfn, where, size, *val);
+		return ret;
+	}
 
 	if (!mvebu_pcie_link_up(port)) {
 		*val = 0xffffffff;
@@ -1156,6 +1165,8 @@  static int mvebu_pcie_parse_request_resources(struct mvebu_pcie *pcie)
 	/* Get the PCIe IO aperture */
 	mvebu_mbus_get_pcie_io_aperture(&pcie->io);
 
+	dev_info(dev, "MEM: %pR, IO: %pR\n", &pcie->mem, &pcie->io);
+
 	if (resource_size(&pcie->io) != 0) {
 		pcie->realio.flags = pcie->io.flags;
 		pcie->realio.start = PCIBIOS_MIN_IO;
-- 
2.20.1