Patchwork ARM: dts: ls1021a: Add memory controller

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Submitter Patrick Havelange
Date Dec. 11, 2018, 3:48 p.m.
Message ID <20181211154834.4489-1-patrick.havelange@essensium.com>
Download mbox | patch
Permalink /patch/678199/
State New
Headers show

Comments

Patrick Havelange - Dec. 11, 2018, 3:48 p.m.
The LS1021A has a memory controller that supports EDAC. This commit
adds an entry for it.

Signed-off-by: Patrick Havelange <patrick.havelange@essensium.com>
---
 arch/arm/boot/dts/ls1021a.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)
Shawn Guo - Jan. 10, 2019, 7:03 a.m.
On Tue, Dec 11, 2018 at 04:48:34PM +0100, Patrick Havelange wrote:
> The LS1021A has a memory controller that supports EDAC. This commit
> adds an entry for it.
> 
> Signed-off-by: Patrick Havelange <patrick.havelange@essensium.com>

Applied, thanks.

Patch

diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index bdd6e66a79ad..a877c32bff20 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -125,6 +125,13 @@ 
 		interrupt-parent = <&gic>;
 		ranges;
 
+		ddr: memory-controller@1080000 {
+			compatible = "fsl,qoriq-memory-controller";
+			reg = <0x0 0x1080000 0x0 0x1000>;
+			interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+			big-endian;
+		};
+
 		gic: interrupt-controller@1400000 {
 			compatible = "arm,gic-400", "arm,cortex-a7-gic";
 			#interrupt-cells = <3>;