Patchwork [v2] dmaengine: dw: Fix FIFO size for Intel Merrifield

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Submitter Andy Shevchenko
Date Dec. 5, 2018, 4:33 p.m.
Message ID <20181205163359.45286-1-andriy.shevchenko@linux.intel.com>
Download mbox | patch
Permalink /patch/673337/
State New
Headers show

Comments

Andy Shevchenko - Dec. 5, 2018, 4:33 p.m.
Intel Merrifield has a reduced size of FIFO used in iDMA 32-bit controller,
i.e. 512 bytes instead of 1024.

Fix this by partitioning it as 64 bytes per channel.

Note, in the future we might switch to 'fifo-size' property instead of
hard coded value.

Fixes: 199244d69458 ("dmaengine: dw: add support of iDMA 32-bit hardware")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: stable@vger.kernel.org
---
 drivers/dma/dw/core.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)
Viresh Kumar - Dec. 6, 2018, 4:21 a.m.
On 05-12-18, 18:33, Andy Shevchenko wrote:
> Intel Merrifield has a reduced size of FIFO used in iDMA 32-bit controller,
> i.e. 512 bytes instead of 1024.
> 
> Fix this by partitioning it as 64 bytes per channel.
> 
> Note, in the future we might switch to 'fifo-size' property instead of
> hard coded value.
> 
> Fixes: 199244d69458 ("dmaengine: dw: add support of iDMA 32-bit hardware")
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Cc: stable@vger.kernel.org
> ---
>  drivers/dma/dw/core.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)

Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Vinod Koul - Dec. 6, 2018, 5:24 a.m.
On 05-12-18, 18:33, Andy Shevchenko wrote:
> Intel Merrifield has a reduced size of FIFO used in iDMA 32-bit controller,
> i.e. 512 bytes instead of 1024.
> 
> Fix this by partitioning it as 64 bytes per channel.
> 
> Note, in the future we might switch to 'fifo-size' property instead of
> hard coded value.

Applied, thanks

Patch

diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c
index 2c5ca1961256..dc053e62f894 100644
--- a/drivers/dma/dw/core.c
+++ b/drivers/dma/dw/core.c
@@ -1061,12 +1061,12 @@  static void dwc_issue_pending(struct dma_chan *chan)
 /*
  * Program FIFO size of channels.
  *
- * By default full FIFO (1024 bytes) is assigned to channel 0. Here we
+ * By default full FIFO (512 bytes) is assigned to channel 0. Here we
  * slice FIFO on equal parts between channels.
  */
 static void idma32_fifo_partition(struct dw_dma *dw)
 {
-	u64 value = IDMA32C_FP_PSIZE_CH0(128) | IDMA32C_FP_PSIZE_CH1(128) |
+	u64 value = IDMA32C_FP_PSIZE_CH0(64) | IDMA32C_FP_PSIZE_CH1(64) |
 		    IDMA32C_FP_UPDATE;
 	u64 fifo_partition = 0;
 
@@ -1079,7 +1079,7 @@  static void idma32_fifo_partition(struct dw_dma *dw)
 	/* Fill FIFO_PARTITION high bits (Channels 2..3, 6..7) */
 	fifo_partition |= value << 32;
 
-	/* Program FIFO Partition registers - 128 bytes for each channel */
+	/* Program FIFO Partition registers - 64 bytes per channel */
 	idma32_writeq(dw, FIFO_PARTITION1, fifo_partition);
 	idma32_writeq(dw, FIFO_PARTITION0, fifo_partition);
 }