Patchwork WIP: UFS on apq8098

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Submitter Marc Gonzalez
Date Dec. 3, 2018, 4:53 p.m.
Message ID <2b186a33-aea2-629c-6fbf-aefe16ff7b0a@free.fr>
Download mbox | patch
Permalink /patch/670915/
State New
Headers show

Comments

Marc Gonzalez - Dec. 3, 2018, 4:53 p.m.
On 03/12/2018 16:18, Marc Gonzalez wrote:

> I'm trying to enable UFS on apq8098. Just wanted to share my progress
> so far, in case someone spots any glaring mistakes.
> 
> rpm_smd_clk_probe() runs successfully, and returns 0.
> 
> qcom_qmp_phy_probe() fails:
> 
> [    0.913707] qcom-qmp-phy 1da7000.phy: Failed to get clk 'ref': -2
> [    0.913761] qcom-qmp-phy: probe of 1da7000.phy failed with error -2
> 
> ufs_qcom_probe() also fails (which may be caused by PHY failure)
> 
> [    2.368486] ufshcd-qcom 1da4000.ufshc: ufshcd_get_vreg: vdd-hba get failed, err=-517
> [    2.370673] ufshcd-qcom 1da4000.ufshc: Initialization failed
> [    2.412908] ufshcd-qcom 1da4000.ufshc: ufshcd_pltfrm_init() failed -517

Having solved these trivial issues, I hit other issues later on.
(Full diff provided below, including code from Bjorn and Jeffrey)

Relevant logs:

[    0.970565] qcom-qmp-phy 1da7000.phy: Linked as a consumer to regulator.15
[    0.970676] qcom-qmp-phy 1da7000.phy: Linked as a consumer to regulator.16
[    0.971349] qcom-qmp-phy 1da7000.phy: Registered Qcom-QMP phy
[    2.293324] ufshcd-qcom 1da4000.ufshc: ufshcd_populate_vreg: Unable to find vdd-hba-supply regulator, assuming enabled
[    2.355902] ufshcd-qcom 1da4000.ufshc: Linked as a consumer to regulator.34
[    2.359197] ufshcd-qcom 1da4000.ufshc: Linked as a consumer to regulator.40
[    2.365857] ufshcd-qcom 1da4000.ufshc: Linked as a consumer to regulator.5
[    2.400665] scsi host0: ufshcd
[    2.435181] ufshcd-qcom 1da4000.ufshc: ufshcd_print_pwr_info:[RX, TX]: gear=[1, 1], lane[1, 1], pwr[SLOWAUTO_MODE, SLOWAUTO_MODE], rate = 0
[    3.968211] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag: Sending flag query for idn 1 failed, err = -11
[    5.472133] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag: Sending flag query for idn 1 failed, err = -11
[    6.976114] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag: Sending flag query for idn 1 failed, err = -11
[    6.976387] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag_retry: query attribute, opcode 6, idn 1, failed with error -11 after 3 retires
[    6.984999] ufshcd-qcom 1da4000.ufshc: ufshcd_complete_dev_init setting fDeviceInit flag failed with error -11

I will investigate :-)

Regards.
Marc Gonzalez - Dec. 4, 2018, 3:23 p.m.
On 03/12/2018 17:53, Marc Gonzalez wrote:

> [    0.970565] qcom-qmp-phy 1da7000.phy: Linked as a consumer to regulator.15
> [    0.970676] qcom-qmp-phy 1da7000.phy: Linked as a consumer to regulator.16
> [    0.971349] qcom-qmp-phy 1da7000.phy: Registered Qcom-QMP phy
> [    2.293324] ufshcd-qcom 1da4000.ufshc: ufshcd_populate_vreg: Unable to find vdd-hba-supply regulator, assuming enabled
> [    2.355902] ufshcd-qcom 1da4000.ufshc: Linked as a consumer to regulator.34
> [    2.359197] ufshcd-qcom 1da4000.ufshc: Linked as a consumer to regulator.40
> [    2.365857] ufshcd-qcom 1da4000.ufshc: Linked as a consumer to regulator.5
> [    2.400665] scsi host0: ufshcd
> [    2.435181] ufshcd-qcom 1da4000.ufshc: ufshcd_print_pwr_info:[RX, TX]: gear=[1, 1], lane[1, 1], pwr[SLOWAUTO_MODE, SLOWAUTO_MODE], rate = 0
> [    3.968211] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag: Sending flag query for idn 1 failed, err = -11
> [    5.472133] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag: Sending flag query for idn 1 failed, err = -11
> [    6.976114] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag: Sending flag query for idn 1 failed, err = -11
> [    6.976387] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag_retry: query attribute, opcode 6, idn 1, failed with error -11 after 3 retires
> [    6.984999] ufshcd-qcom 1da4000.ufshc: ufshcd_complete_dev_init setting fDeviceInit flag failed with error -11

The PHY and MAC init *seem* successful, but obviously something goes wrong,
since the query times out after 1500 ms, waiting for the completion in
ufshcd_wait_for_dev_cmd()

#define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */

err is set to -ETIMEDOUT (i.e. -110) then the command is cleared for an
ulterior retry, and err is set to -EAGAIN (i.e. -11)

The question is: why does the command time out?

Enabling DEBUG...

[    2.046246] ufshcd-qcom 1da4000.ufshc: ufshcd_populate_vreg: Unable to find vdd-hba-supply regulator, assuming enabled
[    2.046675] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: core_clk, rate: 198400000
[    2.056101] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: bus_aggr_clk, rate: 198400000
[    2.064333] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: iface_clk, rate: 0
[    2.072820] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: core_clk_unipro, rate: 0
[    2.080304] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: core_clk_ice, rate: 0
[    2.088547] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: ref_clk, rate: 0
[    2.096269] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: tx_lane0_sync_clk, rate: 0
[    2.103743] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: rx_lane0_sync_clk, rate: 0
[    2.111812] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: rx_lane1_sync_clk, rate: 0
[    2.120178] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: core_clk enabled
[    2.128292] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: bus_aggr_clk enabled
[    2.135848] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: iface_clk enabled
[    2.143833] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: core_clk_unipro enabled
[    2.151831] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: core_clk_ice enabled
[    2.160312] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: ref_clk enabled
[    2.167789] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: tx_lane0_sync_clk enabled
[    2.175444] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: rx_lane0_sync_clk enabled
[    2.184043] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: rx_lane1_sync_clk enabled
[    2.201054] ufshcd-qcom 1da4000.ufshc: Linked as a consumer to regulator.34
[    2.204116] ufshcd-qcom 1da4000.ufshc: Linked as a consumer to regulator.40
[    2.210800] ufshcd-qcom 1da4000.ufshc: Linked as a consumer to regulator.5

The zero clock rates look suspicious, don't they?

[    2.255243] ufshcd-qcom 1da4000.ufshc: ufshcd_print_pwr_info:[RX, TX]: gear=[1, 1], lane[1, 1], pwr[SLOWAUTO_MODE, SLOWAUTO_MODE], rate = 0
[    2.256240] ufshcd_wait_for_dev_cmd: time_left=8
[    2.266734] ufshcd_wait_for_dev_cmd = 0

This command succeeds.

[    3.780315] ufshcd_wait_for_dev_cmd: time_left=0
[    3.780484] ufshcd-qcom 1da4000.ufshc: ufshcd_wait_for_dev_cmd: dev_cmd request timedout, tag 31
[    3.784258] ufshcd_wait_for_dev_cmd = -11
[    3.792949] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag: Sending flag query for idn 1 failed, err = -11
[    3.796936] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag_retry: failed with error -11, retries 0
[    3.872239] ufshcd-qcom 1da4000.ufshc: ufshcd_update_uic_error: UIC error flags = 0x00000000
[    3.935871] ufshcd-qcom 1da4000.ufshc: ufshcd_update_uic_error: UIC error flags = 0x00000000
[    4.006340] ufshcd-qcom 1da4000.ufshc: ufshcd_update_uic_error: UIC error flags = 0x00000001
[    5.316263] ufshcd_wait_for_dev_cmd: time_left=0
[    5.316406] ufshcd-qcom 1da4000.ufshc: ufshcd_wait_for_dev_cmd: dev_cmd request timedout, tag 31
[    5.320177] ufshcd_wait_for_dev_cmd = -11
[    5.328838] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag: Sending flag query for idn 1 failed, err = -11
[    5.332872] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag_retry: failed with error -11, retries 1
[    6.852272] ufshcd_wait_for_dev_cmd: time_left=0
[    6.852415] ufshcd-qcom 1da4000.ufshc: ufshcd_wait_for_dev_cmd: dev_cmd request timedout, tag 31
[    6.856185] ufshcd_wait_for_dev_cmd = -11
[    6.864846] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag: Sending flag query for idn 1 failed, err = -11
[    6.868872] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag_retry: failed with error -11, retries 2
[    6.878415] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag_retry: query attribute, opcode 6, idn 1, failed with error -11 after 3 retires
[    6.887258] ufshcd-qcom 1da4000.ufshc: ufshcd_complete_dev_init setting fDeviceInit flag failed with error -11
[    6.900929] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: core_clk disabled
[    6.909171] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: bus_aggr_clk disabled
[    6.917054] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: iface_clk disabled
[    6.925112] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: core_clk_unipro disabled
[    6.932849] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: core_clk_ice disabled
[    6.941305] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: ref_clk disabled
[    6.949346] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: tx_lane0_sync_clk disabled
[    6.956721] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: rx_lane0_sync_clk disabled
[    6.965405] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: rx_lane1_sync_clk disabled

It's strange that one command succeeds, and the 3 next fail...
Maybe they don't speak to the same HW block...

Regards.
Jeffrey Hugo - Dec. 4, 2018, 3:45 p.m.
On 12/4/2018 8:23 AM, Marc Gonzalez wrote:
> On 03/12/2018 17:53, Marc Gonzalez wrote:
> 
>> [    0.970565] qcom-qmp-phy 1da7000.phy: Linked as a consumer to regulator.15
>> [    0.970676] qcom-qmp-phy 1da7000.phy: Linked as a consumer to regulator.16
>> [    0.971349] qcom-qmp-phy 1da7000.phy: Registered Qcom-QMP phy
>> [    2.293324] ufshcd-qcom 1da4000.ufshc: ufshcd_populate_vreg: Unable to find vdd-hba-supply regulator, assuming enabled
>> [    2.355902] ufshcd-qcom 1da4000.ufshc: Linked as a consumer to regulator.34
>> [    2.359197] ufshcd-qcom 1da4000.ufshc: Linked as a consumer to regulator.40
>> [    2.365857] ufshcd-qcom 1da4000.ufshc: Linked as a consumer to regulator.5
>> [    2.400665] scsi host0: ufshcd
>> [    2.435181] ufshcd-qcom 1da4000.ufshc: ufshcd_print_pwr_info:[RX, TX]: gear=[1, 1], lane[1, 1], pwr[SLOWAUTO_MODE, SLOWAUTO_MODE], rate = 0
>> [    3.968211] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag: Sending flag query for idn 1 failed, err = -11
>> [    5.472133] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag: Sending flag query for idn 1 failed, err = -11
>> [    6.976114] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag: Sending flag query for idn 1 failed, err = -11
>> [    6.976387] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag_retry: query attribute, opcode 6, idn 1, failed with error -11 after 3 retires
>> [    6.984999] ufshcd-qcom 1da4000.ufshc: ufshcd_complete_dev_init setting fDeviceInit flag failed with error -11
> 
> The PHY and MAC init *seem* successful, but obviously something goes wrong,
> since the query times out after 1500 ms, waiting for the completion in
> ufshcd_wait_for_dev_cmd()
> 
> #define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */
> 
> err is set to -ETIMEDOUT (i.e. -110) then the command is cleared for an
> ulterior retry, and err is set to -EAGAIN (i.e. -11)
> 
> The question is: why does the command time out?
> 
> Enabling DEBUG...
> 
> [    2.046246] ufshcd-qcom 1da4000.ufshc: ufshcd_populate_vreg: Unable to find vdd-hba-supply regulator, assuming enabled
> [    2.046675] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: core_clk, rate: 198400000
> [    2.056101] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: bus_aggr_clk, rate: 198400000
> [    2.064333] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: iface_clk, rate: 0
> [    2.072820] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: core_clk_unipro, rate: 0
> [    2.080304] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: core_clk_ice, rate: 0
> [    2.088547] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: ref_clk, rate: 0
> [    2.096269] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: tx_lane0_sync_clk, rate: 0
> [    2.103743] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: rx_lane0_sync_clk, rate: 0
> [    2.111812] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: rx_lane1_sync_clk, rate: 0
> [    2.120178] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: core_clk enabled
> [    2.128292] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: bus_aggr_clk enabled
> [    2.135848] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: iface_clk enabled
> [    2.143833] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: core_clk_unipro enabled
> [    2.151831] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: core_clk_ice enabled
> [    2.160312] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: ref_clk enabled
> [    2.167789] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: tx_lane0_sync_clk enabled
> [    2.175444] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: rx_lane0_sync_clk enabled
> [    2.184043] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: rx_lane1_sync_clk enabled
> [    2.201054] ufshcd-qcom 1da4000.ufshc: Linked as a consumer to regulator.34
> [    2.204116] ufshcd-qcom 1da4000.ufshc: Linked as a consumer to regulator.40
> [    2.210800] ufshcd-qcom 1da4000.ufshc: Linked as a consumer to regulator.5
> 
> The zero clock rates look suspicious, don't they?
> 
> [    2.255243] ufshcd-qcom 1da4000.ufshc: ufshcd_print_pwr_info:[RX, TX]: gear=[1, 1], lane[1, 1], pwr[SLOWAUTO_MODE, SLOWAUTO_MODE], rate = 0
> [    2.256240] ufshcd_wait_for_dev_cmd: time_left=8
> [    2.266734] ufshcd_wait_for_dev_cmd = 0
> 
> This command succeeds.
> 
> [    3.780315] ufshcd_wait_for_dev_cmd: time_left=0
> [    3.780484] ufshcd-qcom 1da4000.ufshc: ufshcd_wait_for_dev_cmd: dev_cmd request timedout, tag 31
> [    3.784258] ufshcd_wait_for_dev_cmd = -11
> [    3.792949] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag: Sending flag query for idn 1 failed, err = -11
> [    3.796936] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag_retry: failed with error -11, retries 0
> [    3.872239] ufshcd-qcom 1da4000.ufshc: ufshcd_update_uic_error: UIC error flags = 0x00000000
> [    3.935871] ufshcd-qcom 1da4000.ufshc: ufshcd_update_uic_error: UIC error flags = 0x00000000
> [    4.006340] ufshcd-qcom 1da4000.ufshc: ufshcd_update_uic_error: UIC error flags = 0x00000001
> [    5.316263] ufshcd_wait_for_dev_cmd: time_left=0
> [    5.316406] ufshcd-qcom 1da4000.ufshc: ufshcd_wait_for_dev_cmd: dev_cmd request timedout, tag 31
> [    5.320177] ufshcd_wait_for_dev_cmd = -11
> [    5.328838] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag: Sending flag query for idn 1 failed, err = -11
> [    5.332872] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag_retry: failed with error -11, retries 1
> [    6.852272] ufshcd_wait_for_dev_cmd: time_left=0
> [    6.852415] ufshcd-qcom 1da4000.ufshc: ufshcd_wait_for_dev_cmd: dev_cmd request timedout, tag 31
> [    6.856185] ufshcd_wait_for_dev_cmd = -11
> [    6.864846] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag: Sending flag query for idn 1 failed, err = -11
> [    6.868872] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag_retry: failed with error -11, retries 2
> [    6.878415] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag_retry: query attribute, opcode 6, idn 1, failed with error -11 after 3 retires
> [    6.887258] ufshcd-qcom 1da4000.ufshc: ufshcd_complete_dev_init setting fDeviceInit flag failed with error -11
> [    6.900929] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: core_clk disabled
> [    6.909171] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: bus_aggr_clk disabled
> [    6.917054] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: iface_clk disabled
> [    6.925112] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: core_clk_unipro disabled
> [    6.932849] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: core_clk_ice disabled
> [    6.941305] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: ref_clk disabled
> [    6.949346] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: tx_lane0_sync_clk disabled
> [    6.956721] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: rx_lane0_sync_clk disabled
> [    6.965405] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: rx_lane1_sync_clk disabled
> 
> It's strange that one command succeeds, and the 3 next fail...
> Maybe they don't speak to the same HW block...

Throwing something at a wall and seeing if it sticks....

The downstream MTP dtsi has -

&ufsphy1 {
         vdda-phy-supply = <&pm8998_l1>;
         vdda-pll-supply = <&pm8998_l2>;
         vddp-ref-clk-supply = <&pm8998_l26>;
         vdda-phy-max-microamp = <51400>;
         vdda-pll-max-microamp = <14600>;
         vddp-ref-clk-max-microamp = <100>;
         vddp-ref-clk-always-on;
         status = "ok";
};

&ufs1 {
         vdd-hba-supply = <&gdsc_ufs>;
         vdd-hba-fixed-regulator;
         vcc-supply = <&pm8998_l20>;
         vccq-supply = <&pm8998_l26>;
         vccq2-supply = <&pm8998_s4>;
         vcc-max-microamp = <750000>;
         vccq-max-microamp = <560000>;
         vccq2-max-microamp = <750000>;
         status = "ok";
};


The *-max-microamp fields are basically load values that the downstream 
driver sets on the regulators to ensure they are in a performance mode 
before the driver attempts normal operation.

On the corresponding regulators in the mtp dtsi, you might try adding
regulator-allow-set-load;
regulator-system-load = <X>;

It might be that the regulators act as pull ups on some of the 
signal/data lines, and by default they are not being driven hard enough 
to do that job properly, resulting in the timeouts you see.
Jeffrey Hugo - Dec. 4, 2018, 4:14 p.m.
On 12/4/2018 8:45 AM, Jeffrey Hugo wrote:
> On 12/4/2018 8:23 AM, Marc Gonzalez wrote:
>> On 03/12/2018 17:53, Marc Gonzalez wrote:
>>
>>> [    0.970565] qcom-qmp-phy 1da7000.phy: Linked as a consumer to 
>>> regulator.15
>>> [    0.970676] qcom-qmp-phy 1da7000.phy: Linked as a consumer to 
>>> regulator.16
>>> [    0.971349] qcom-qmp-phy 1da7000.phy: Registered Qcom-QMP phy
>>> [    2.293324] ufshcd-qcom 1da4000.ufshc: ufshcd_populate_vreg: 
>>> Unable to find vdd-hba-supply regulator, assuming enabled
>>> [    2.355902] ufshcd-qcom 1da4000.ufshc: Linked as a consumer to 
>>> regulator.34
>>> [    2.359197] ufshcd-qcom 1da4000.ufshc: Linked as a consumer to 
>>> regulator.40
>>> [    2.365857] ufshcd-qcom 1da4000.ufshc: Linked as a consumer to 
>>> regulator.5
>>> [    2.400665] scsi host0: ufshcd
>>> [    2.435181] ufshcd-qcom 1da4000.ufshc: ufshcd_print_pwr_info:[RX, 
>>> TX]: gear=[1, 1], lane[1, 1], pwr[SLOWAUTO_MODE, SLOWAUTO_MODE], rate 
>>> = 0
>>> [    3.968211] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag: Sending 
>>> flag query for idn 1 failed, err = -11
>>> [    5.472133] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag: Sending 
>>> flag query for idn 1 failed, err = -11
>>> [    6.976114] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag: Sending 
>>> flag query for idn 1 failed, err = -11
>>> [    6.976387] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag_retry: 
>>> query attribute, opcode 6, idn 1, failed with error -11 after 3 retires
>>> [    6.984999] ufshcd-qcom 1da4000.ufshc: ufshcd_complete_dev_init 
>>> setting fDeviceInit flag failed with error -11
>>
>> The PHY and MAC init *seem* successful, but obviously something goes 
>> wrong,
>> since the query times out after 1500 ms, waiting for the completion in
>> ufshcd_wait_for_dev_cmd()
>>
>> #define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */
>>
>> err is set to -ETIMEDOUT (i.e. -110) then the command is cleared for an
>> ulterior retry, and err is set to -EAGAIN (i.e. -11)
>>
>> The question is: why does the command time out?
>>
>> Enabling DEBUG...
>>
>> [    2.046246] ufshcd-qcom 1da4000.ufshc: ufshcd_populate_vreg: Unable 
>> to find vdd-hba-supply regulator, assuming enabled
>> [    2.046675] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: 
>> core_clk, rate: 198400000
>> [    2.056101] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: 
>> bus_aggr_clk, rate: 198400000
>> [    2.064333] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: 
>> iface_clk, rate: 0
>> [    2.072820] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: 
>> core_clk_unipro, rate: 0
>> [    2.080304] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: 
>> core_clk_ice, rate: 0
>> [    2.088547] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: 
>> ref_clk, rate: 0
>> [    2.096269] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: 
>> tx_lane0_sync_clk, rate: 0
>> [    2.103743] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: 
>> rx_lane0_sync_clk, rate: 0
>> [    2.111812] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: 
>> rx_lane1_sync_clk, rate: 0
>> [    2.120178] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: 
>> core_clk enabled
>> [    2.128292] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: 
>> bus_aggr_clk enabled
>> [    2.135848] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: 
>> iface_clk enabled
>> [    2.143833] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: 
>> core_clk_unipro enabled
>> [    2.151831] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: 
>> core_clk_ice enabled
>> [    2.160312] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: 
>> ref_clk enabled
>> [    2.167789] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: 
>> tx_lane0_sync_clk enabled
>> [    2.175444] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: 
>> rx_lane0_sync_clk enabled
>> [    2.184043] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: 
>> rx_lane1_sync_clk enabled
>> [    2.201054] ufshcd-qcom 1da4000.ufshc: Linked as a consumer to 
>> regulator.34
>> [    2.204116] ufshcd-qcom 1da4000.ufshc: Linked as a consumer to 
>> regulator.40
>> [    2.210800] ufshcd-qcom 1da4000.ufshc: Linked as a consumer to 
>> regulator.5
>>
>> The zero clock rates look suspicious, don't they?
>>
>> [    2.255243] ufshcd-qcom 1da4000.ufshc: ufshcd_print_pwr_info:[RX, 
>> TX]: gear=[1, 1], lane[1, 1], pwr[SLOWAUTO_MODE, SLOWAUTO_MODE], rate = 0
>> [    2.256240] ufshcd_wait_for_dev_cmd: time_left=8
>> [    2.266734] ufshcd_wait_for_dev_cmd = 0
>>
>> This command succeeds.
>>
>> [    3.780315] ufshcd_wait_for_dev_cmd: time_left=0
>> [    3.780484] ufshcd-qcom 1da4000.ufshc: ufshcd_wait_for_dev_cmd: 
>> dev_cmd request timedout, tag 31
>> [    3.784258] ufshcd_wait_for_dev_cmd = -11
>> [    3.792949] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag: Sending 
>> flag query for idn 1 failed, err = -11
>> [    3.796936] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag_retry: 
>> failed with error -11, retries 0
>> [    3.872239] ufshcd-qcom 1da4000.ufshc: ufshcd_update_uic_error: UIC 
>> error flags = 0x00000000
>> [    3.935871] ufshcd-qcom 1da4000.ufshc: ufshcd_update_uic_error: UIC 
>> error flags = 0x00000000
>> [    4.006340] ufshcd-qcom 1da4000.ufshc: ufshcd_update_uic_error: UIC 
>> error flags = 0x00000001
>> [    5.316263] ufshcd_wait_for_dev_cmd: time_left=0
>> [    5.316406] ufshcd-qcom 1da4000.ufshc: ufshcd_wait_for_dev_cmd: 
>> dev_cmd request timedout, tag 31
>> [    5.320177] ufshcd_wait_for_dev_cmd = -11
>> [    5.328838] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag: Sending 
>> flag query for idn 1 failed, err = -11
>> [    5.332872] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag_retry: 
>> failed with error -11, retries 1
>> [    6.852272] ufshcd_wait_for_dev_cmd: time_left=0
>> [    6.852415] ufshcd-qcom 1da4000.ufshc: ufshcd_wait_for_dev_cmd: 
>> dev_cmd request timedout, tag 31
>> [    6.856185] ufshcd_wait_for_dev_cmd = -11
>> [    6.864846] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag: Sending 
>> flag query for idn 1 failed, err = -11
>> [    6.868872] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag_retry: 
>> failed with error -11, retries 2
>> [    6.878415] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag_retry: 
>> query attribute, opcode 6, idn 1, failed with error -11 after 3 retires
>> [    6.887258] ufshcd-qcom 1da4000.ufshc: ufshcd_complete_dev_init 
>> setting fDeviceInit flag failed with error -11
>> [    6.900929] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: 
>> core_clk disabled
>> [    6.909171] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: 
>> bus_aggr_clk disabled
>> [    6.917054] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: 
>> iface_clk disabled
>> [    6.925112] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: 
>> core_clk_unipro disabled
>> [    6.932849] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: 
>> core_clk_ice disabled
>> [    6.941305] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: 
>> ref_clk disabled
>> [    6.949346] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: 
>> tx_lane0_sync_clk disabled
>> [    6.956721] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: 
>> rx_lane0_sync_clk disabled
>> [    6.965405] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: 
>> rx_lane1_sync_clk disabled
>>
>> It's strange that one command succeeds, and the 3 next fail...
>> Maybe they don't speak to the same HW block...
> 
> Throwing something at a wall and seeing if it sticks....
> 
> The downstream MTP dtsi has -
> 
> &ufsphy1 {
>          vdda-phy-supply = <&pm8998_l1>;
>          vdda-pll-supply = <&pm8998_l2>;
>          vddp-ref-clk-supply = <&pm8998_l26>;
>          vdda-phy-max-microamp = <51400>;
>          vdda-pll-max-microamp = <14600>;
>          vddp-ref-clk-max-microamp = <100>;
>          vddp-ref-clk-always-on;
>          status = "ok";
> };
> 
> &ufs1 {
>          vdd-hba-supply = <&gdsc_ufs>;
>          vdd-hba-fixed-regulator;
>          vcc-supply = <&pm8998_l20>;
>          vccq-supply = <&pm8998_l26>;
>          vccq2-supply = <&pm8998_s4>;
>          vcc-max-microamp = <750000>;
>          vccq-max-microamp = <560000>;
>          vccq2-max-microamp = <750000>;
>          status = "ok";
> };
> 
> 
> The *-max-microamp fields are basically load values that the downstream 
> driver sets on the regulators to ensure they are in a performance mode 
> before the driver attempts normal operation.
> 
> On the corresponding regulators in the mtp dtsi, you might try adding
> regulator-allow-set-load;
> regulator-system-load = <X>;
> 
> It might be that the regulators act as pull ups on some of the 
> signal/data lines, and by default they are not being driven hard enough 
> to do that job properly, resulting in the timeouts you see.
> 

Nevermind, the mainline driver actually does this.  Although I suppose 
out of paranoia, you could double check that the load is being set on 
the regulator as expected.  IIRC, you can do that in sysfs.
Marc Gonzalez - Dec. 4, 2018, 4:17 p.m.
On 04/12/2018 16:23, Marc Gonzalez wrote:

> [    2.046246] ufshcd-qcom 1da4000.ufshc: ufshcd_populate_vreg: Unable to find vdd-hba-supply regulator, assuming enabled
> [    2.046675] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: core_clk, rate: 198400000
> [    2.056101] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: bus_aggr_clk, rate: 198400000
> [    2.064333] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: iface_clk, rate: 0
> [    2.072820] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: core_clk_unipro, rate: 0
> [    2.080304] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: core_clk_ice, rate: 0
> [    2.088547] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: ref_clk, rate: 0
> [    2.096269] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: tx_lane0_sync_clk, rate: 0
> [    2.103743] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: rx_lane0_sync_clk, rate: 0
> [    2.111812] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: rx_lane1_sync_clk, rate: 0
> [    2.120178] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: core_clk enabled
> [    2.128292] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: bus_aggr_clk enabled
> [    2.135848] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: iface_clk enabled
> [    2.143833] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: core_clk_unipro enabled
> [    2.151831] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: core_clk_ice enabled
> [    2.160312] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: ref_clk enabled
> [    2.167789] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: tx_lane0_sync_clk enabled
> [    2.175444] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: rx_lane0_sync_clk enabled
> [    2.184043] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: rx_lane1_sync_clk enabled
> [    2.201054] ufshcd-qcom 1da4000.ufshc: Linked as a consumer to regulator.34
> [    2.204116] ufshcd-qcom 1da4000.ufshc: Linked as a consumer to regulator.40
> [    2.210800] ufshcd-qcom 1da4000.ufshc: Linked as a consumer to regulator.5
> [    2.255243] ufshcd-qcom 1da4000.ufshc: ufshcd_print_pwr_info:[RX, TX]: gear=[1, 1], lane[1, 1], pwr[SLOWAUTO_MODE, SLOWAUTO_MODE], rate = 0
> [    2.256240] ufshcd_wait_for_dev_cmd: time_left=8
> [    2.266734] ufshcd_wait_for_dev_cmd = 0
> [    3.780315] ufshcd_wait_for_dev_cmd: time_left=0
> [    3.780484] ufshcd-qcom 1da4000.ufshc: ufshcd_wait_for_dev_cmd: dev_cmd request timedout, tag 31
> [    3.784258] ufshcd_wait_for_dev_cmd = -11
> [    3.792949] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag: Sending flag query for idn 1 failed, err = -11
> [    3.796936] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag_retry: failed with error -11, retries 0
> [    3.872239] ufshcd-qcom 1da4000.ufshc: ufshcd_update_uic_error: UIC error flags = 0x00000000
> [    3.935871] ufshcd-qcom 1da4000.ufshc: ufshcd_update_uic_error: UIC error flags = 0x00000000
> [    4.006340] ufshcd-qcom 1da4000.ufshc: ufshcd_update_uic_error: UIC error flags = 0x00000001
> [    5.316263] ufshcd_wait_for_dev_cmd: time_left=0
> [    5.316406] ufshcd-qcom 1da4000.ufshc: ufshcd_wait_for_dev_cmd: dev_cmd request timedout, tag 31
> [    5.320177] ufshcd_wait_for_dev_cmd = -11
> [    5.328838] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag: Sending flag query for idn 1 failed, err = -11
> [    5.332872] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag_retry: failed with error -11, retries 1
> [    6.852272] ufshcd_wait_for_dev_cmd: time_left=0
> [    6.852415] ufshcd-qcom 1da4000.ufshc: ufshcd_wait_for_dev_cmd: dev_cmd request timedout, tag 31
> [    6.856185] ufshcd_wait_for_dev_cmd = -11
> [    6.864846] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag: Sending flag query for idn 1 failed, err = -11
> [    6.868872] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag_retry: failed with error -11, retries 2
> [    6.878415] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag_retry: query attribute, opcode 6, idn 1, failed with error -11 after 3 retires
> [    6.887258] ufshcd-qcom 1da4000.ufshc: ufshcd_complete_dev_init setting fDeviceInit flag failed with error -11
> [    6.900929] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: core_clk disabled
> [    6.909171] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: bus_aggr_clk disabled
> [    6.917054] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: iface_clk disabled
> [    6.925112] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: core_clk_unipro disabled
> [    6.932849] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: core_clk_ice disabled
> [    6.941305] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: ref_clk disabled
> [    6.949346] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: tx_lane0_sync_clk disabled
> [    6.956721] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: rx_lane0_sync_clk disabled
> [    6.965405] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: rx_lane1_sync_clk disabled

I booted a downstream kernel with UFS debug enabled (log provided below)

The one difference that jumps out at me is:

DOWNSTREAM
[   10.902119] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: core_clk_unipro, rate: 150000000
[   10.902161] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: core_clk_ice, rate: 300000000
[   10.902198] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: ref_clk, rate: 1000

UPSTREAM
[    2.072820] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: core_clk_unipro, rate: 0
[    2.080304] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: core_clk_ice, rate: 0
[    2.088547] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: ref_clk, rate: 0


Jeffrey, I will check the regulators per your suggestion.
I'm all ears if you have suggestions for the clocks as well.

Regards.


[   10.902030] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: core_clk, rate: 200000000
[   10.902057] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: bus_aggr_clk, rate: 200000000
[   10.902081] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: iface_clk, rate: 0
[   10.902119] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: core_clk_unipro, rate: 150000000
[   10.902161] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: core_clk_ice, rate: 300000000
[   10.902198] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: ref_clk, rate: 1000
[   10.902237] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: tx_lane0_sync_clk, rate: 0
[   10.902276] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: rx_lane0_sync_clk, rate: 0
[   10.902317] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: rx_lane1_sync_clk, rate: 0
[   10.902346] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: core_clk enabled
[   10.902353] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: bus_aggr_clk enabled
[   10.902359] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: iface_clk enabled
[   10.902367] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: core_clk_unipro enabled
[   10.902376] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: core_clk_ice enabled
[   10.902382] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: ref_clk enabled
[   10.902386] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: tx_lane0_sync_clk enabled
[   10.902391] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: rx_lane0_sync_clk enabled
[   10.902395] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: rx_lane1_sync_clk enabled
[   10.905993] ufshcd-qcom 1da4000.ufshc: ufs_qcom_update_sec_cfg: failed, ret -22 scm_ret 0
[   10.906001] ufshcd-qcom 1da4000.ufshc: ufs_qcom_update_sec_cfg: ip: restore_sec_cfg 1, op: restore_sec_cfg 0, ret -22 scm_ret 0
[   10.907535] ufshcd-qcom 1da4000.ufshc: ufs_qcom_parse_reg_info: Unable to find qcom,vddp-ref-clk-supply regulator, assuming enabled
[   10.911697] scsi host0: ufshcd
[   10.918627] qcom_ice 1db0000.ufsice: QC ICE 3.0.65 device found @0xffffff800cde0000
[   10.949115] ufshcd-qcom 1da4000.ufshc: ufshcd_print_pwr_info:[RX, TX]: gear=[1, 1], lane[1, 1], pwr[SLOWAUTO_MODE, SLOWAUTO_MODE], rate = 0
[   10.949860] ufshcd_wait_for_dev_cmd: time_left=3
[   10.949870] ufshcd_wait_for_dev_cmd = 0
[   11.127287] ufshcd_wait_for_dev_cmd: time_left=132
[   11.127304] ufshcd_wait_for_dev_cmd = 0
[   11.127988] ufshcd_wait_for_dev_cmd: time_left=150
[   11.128000] ufshcd_wait_for_dev_cmd = 0
[   11.128937] ufshcd_wait_for_dev_cmd: time_left=150
[   11.128954] ufshcd_wait_for_dev_cmd = 0
[   11.130130] ufshcd_wait_for_dev_cmd: time_left=149
[   11.130145] ufshcd_wait_for_dev_cmd = 0
[   11.131850] ufshcd_wait_for_dev_cmd: time_left=150
[   11.131863] ufshcd_wait_for_dev_cmd = 0
[   11.132574] ufshcd_wait_for_dev_cmd: time_left=150
[   11.132586] ufshcd_wait_for_dev_cmd = 0
[   11.139512] ufshcd-qcom 1da4000.ufshc: ufshcd_print_pwr_info:[RX, TX]: gear=[3, 3], lane[2, 2], pwr[FAST MODE, FAST MODE], rate = 2
[   11.139611] ufshcd_wait_for_dev_cmd: time_left=150
[   11.139615] ufshcd_wait_for_dev_cmd = 0
[   11.139663] ufshcd_wait_for_dev_cmd: time_left=150
[   11.139670] ufshcd_wait_for_dev_cmd = 0
[   11.139680] ufshcd-qcom 1da4000.ufshc: ufshcd_init_icc_levels: setting icc_level 0xf
[   11.139721] ufshcd_wait_for_dev_cmd: time_left=150
[   11.139726] ufshcd_wait_for_dev_cmd = 0
[   11.140594] ufshcd-qcom 1da4000.ufshc: ufshcd_set_queue_depth: activate tcq with queue depth 1
[   11.145001] ufshcd-qcom 1da4000.ufshc: ufshcd_set_queue_depth: activate tcq with queue depth 1
[   11.149027] ufshcd_wait_for_dev_cmd: time_left=150
[   11.149032] ufshcd_wait_for_dev_cmd = 0
[   11.149044] ufshcd-qcom 1da4000.ufshc: ufshcd_set_queue_depth: activate tcq with queue depth 32
[   11.154304] ufshcd_wait_for_dev_cmd: time_left=150
[   11.154310] ufshcd_wait_for_dev_cmd = 0
[   11.154324] ufshcd-qcom 1da4000.ufshc: ufshcd_set_queue_depth: activate tcq with queue depth 32
[   11.157775] ufshcd_wait_for_dev_cmd: time_left=150
[   11.157780] ufshcd_wait_for_dev_cmd = 0
[   11.157793] ufshcd-qcom 1da4000.ufshc: ufshcd_set_queue_depth: activate tcq with queue depth 32
[   11.161038] ufshcd_wait_for_dev_cmd: time_left=150
[   11.161044] ufshcd_wait_for_dev_cmd = 0
[   11.161058] ufshcd-qcom 1da4000.ufshc: ufshcd_set_queue_depth: activate tcq with queue depth 32
[   11.164347] ufshcd_wait_for_dev_cmd: time_left=150
[   11.164353] ufshcd_wait_for_dev_cmd = 0
[   11.164367] ufshcd-qcom 1da4000.ufshc: ufshcd_set_queue_depth: activate tcq with queue depth 32
[   11.167598] ufshcd_wait_for_dev_cmd: time_left=150
[   11.167604] ufshcd_wait_for_dev_cmd = 0
[   11.167618] ufshcd-qcom 1da4000.ufshc: ufshcd_set_queue_depth: activate tcq with queue depth 32
[   11.170837] ufshcd_wait_for_dev_cmd: time_left=150
[   11.170842] ufshcd_wait_for_dev_cmd = 0
[   11.170855] ufshcd-qcom 1da4000.ufshc: ufshcd_set_queue_depth: activate tcq with queue depth 32
[   11.198008] ufshcd-qcom 1da4000.ufshc: __ufshcd_uic_hibern8_enter: Hibern8 Enter at 11197983 us
[   11.198098] ufshcd-qcom 1da4000.ufshc: ufshcd_set_clk_freq: clk: core_clk, rate: 50000000
[   11.198105] ufshcd-qcom 1da4000.ufshc: ufshcd_set_clk_freq: clk: bus_aggr_clk, rate: 50000000
[   11.198111] ufshcd-qcom 1da4000.ufshc: ufshcd_set_clk_freq: clk: iface_clk, rate: 0
[   11.198150] ufshcd-qcom 1da4000.ufshc: ufshcd_set_clk_freq: clk: core_clk_unipro, rate: 37500000
[   11.198184] ufshcd-qcom 1da4000.ufshc: ufshcd_set_clk_freq: clk: core_clk_ice, rate: 75000000
[   11.198193] ufshcd-qcom 1da4000.ufshc: ufshcd_set_clk_freq: clk: ref_clk, rate: 1000
[   11.198199] ufshcd-qcom 1da4000.ufshc: ufshcd_set_clk_freq: clk: tx_lane0_sync_clk, rate: 0
[   11.198205] ufshcd-qcom 1da4000.ufshc: ufshcd_set_clk_freq: clk: rx_lane0_sync_clk, rate: 0
[   11.198210] ufshcd-qcom 1da4000.ufshc: ufshcd_set_clk_freq: clk: rx_lane1_sync_clk, rate: 0
[   11.198879] ufshcd-qcom 1da4000.ufshc: ufshcd_uic_hibern8_exit: Hibern8 Exit at 11198863 us
[   11.227539] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: core_clk disabled
[   11.227546] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: bus_aggr_clk disabled
[   11.227554] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: iface_clk disabled
[   11.227563] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: core_clk_unipro disabled
[   11.227569] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: core_clk_ice disabled
[   11.227575] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: ref_clk disabled
[   11.227578] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: tx_lane0_sync_clk disabled
[   11.227582] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: rx_lane0_sync_clk disabled
[   11.227586] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: rx_lane1_sync_clk disabled
[   11.242041] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: core_clk enabled
[   11.242053] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: bus_aggr_clk enabled
[   11.242065] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: iface_clk enabled
[   11.242087] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: core_clk_unipro enabled
[   11.242109] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: core_clk_ice enabled
[   11.242122] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: ref_clk enabled
[   11.242132] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: tx_lane0_sync_clk enabled
[   11.242143] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: rx_lane0_sync_clk enabled
[   11.242155] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: rx_lane1_sync_clk enabled
[   11.256394] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: core_clk disabled
[   11.256402] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: bus_aggr_clk disabled
[   11.256408] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: iface_clk disabled
[   11.256420] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: core_clk_unipro disabled
[   11.256432] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: core_clk_ice disabled
[   11.256438] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: ref_clk disabled
[   11.256447] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: tx_lane0_sync_clk disabled
[   11.256452] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: rx_lane0_sync_clk disabled
[   11.256459] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: rx_lane1_sync_clk disabled
[   14.194451] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: core_clk enabled
[   14.194489] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: bus_aggr_clk enabled
[   14.200933] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: iface_clk enabled
[   14.208734] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: core_clk_unipro enabled
[   14.216210] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: core_clk_ice enabled
[   14.224450] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: ref_clk enabled
[   14.232171] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: tx_lane0_sync_clk enabled
[   14.239633] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: rx_lane0_sync_clk enabled
[   14.247713] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: rx_lane1_sync_clk enabled
[   14.269093] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: core_clk disabled
[   14.271502] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: bus_aggr_clk disabled
[   14.287195] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: iface_clk disabled
[   14.291435] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: core_clk_unipro disabled
[   14.298666] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: core_clk_ice disabled
[   14.307033] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: ref_clk disabled
[   14.314820] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: tx_lane0_sync_clk disabled
[   14.322484] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: rx_lane0_sync_clk disabled
[   14.330536] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: rx_lane1_sync_clk disabled
[   14.725012] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: core_clk enabled
[   14.725066] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: bus_aggr_clk enabled
[   14.731732] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: iface_clk enabled
[   14.739323] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: core_clk_unipro enabled
[   14.747247] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: core_clk_ice enabled
[   14.755486] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: ref_clk enabled
[   14.770343] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: tx_lane0_sync_clk enabled
[   14.793188] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: rx_lane0_sync_clk enabled
[   14.801080] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: rx_lane1_sync_clk enabled
[   14.815579] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   14.815644] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   14.816320] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   14.816419] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   14.816466] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   14.816596] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   14.840620] ufshcd-qcom 1da4000.ufshc: __ufshcd_uic_hibern8_enter: Hibern8 Enter at 14840602 us
[   14.840834] ufshcd-qcom 1da4000.ufshc: ufshcd_set_clk_freq: clk: core_clk, rate: 200000000
[   14.840837] ufshcd-qcom 1da4000.ufshc: ufshcd_set_clk_freq: clk: bus_aggr_clk, rate: 200000000
[   14.840840] ufshcd-qcom 1da4000.ufshc: ufshcd_set_clk_freq: clk: iface_clk, rate: 0
[   14.840851] ufshcd-qcom 1da4000.ufshc: ufshcd_set_clk_freq: clk: core_clk_unipro, rate: 150000000
[   14.840861] ufshcd-qcom 1da4000.ufshc: ufshcd_set_clk_freq: clk: core_clk_ice, rate: 300000000
[   14.840864] ufshcd-qcom 1da4000.ufshc: ufshcd_set_clk_freq: clk: ref_clk, rate: 1000
[   14.840866] ufshcd-qcom 1da4000.ufshc: ufshcd_set_clk_freq: clk: tx_lane0_sync_clk, rate: 0
[   14.840868] ufshcd-qcom 1da4000.ufshc: ufshcd_set_clk_freq: clk: rx_lane0_sync_clk, rate: 0
[   14.840870] ufshcd-qcom 1da4000.ufshc: ufshcd_set_clk_freq: clk: rx_lane1_sync_clk, rate: 0
[   14.841385] ufshcd-qcom 1da4000.ufshc: ufshcd_uic_hibern8_exit: Hibern8 Exit at 14841370 us
[   14.867089] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   14.867950] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   14.869532] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   14.869857] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   14.875615] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   14.880551] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   14.890984] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   14.892353] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   14.894644] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   14.894988] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   14.895910] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   14.911272] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   14.919013] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   14.970413] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: core_clk disabled
[   14.970426] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: bus_aggr_clk disabled
[   14.970434] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: iface_clk disabled
[   14.970446] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: core_clk_unipro disabled
[   14.970610] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: core_clk_ice disabled
[   14.970615] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: ref_clk disabled
[   14.970622] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: tx_lane0_sync_clk disabled
[   14.970628] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: rx_lane0_sync_clk disabled
[   14.970635] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: rx_lane1_sync_clk disabled
[   15.108525] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: core_clk enabled
[   15.109274] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: bus_aggr_clk enabled
[   15.116973] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: iface_clk enabled
[   15.125152] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: core_clk_unipro enabled
[   15.132215] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: core_clk_ice enabled
[   15.140499] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: ref_clk enabled
[   15.148158] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: tx_lane0_sync_clk enabled
[   15.155642] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: rx_lane0_sync_clk enabled
[   15.163708] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: rx_lane1_sync_clk enabled
[   15.215754] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   15.220335] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   15.220910] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   15.233205] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   15.241491] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   15.263730] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   15.277648] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   15.291173] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   15.292187] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   15.297278] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   15.297737] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   15.300772] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   15.303989] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   15.309161] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   15.320267] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   15.324303] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   15.324971] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   15.334552] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   15.345729] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   15.355783] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   15.364341] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   15.370772] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   15.387535] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   15.394784] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   15.395099] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   15.395367] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   15.412905] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   15.414516] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   15.416494] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   15.422052] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   15.425196] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   15.434301] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   15.434421] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   15.442507] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   15.446766] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   15.450458] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   15.455773] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   15.468107] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   15.471003] ufshcd-qcom 1da4000.ufshc: ufshcd_ioctl: User buffer is NULL!
[   15.519085] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: core_clk disabled
[   15.519131] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: bus_aggr_clk disabled
[   15.525798] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: iface_clk disabled
[   15.533741] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: core_clk_unipro disabled
[   15.541088] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: core_clk_ice disabled
[   15.557222] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: ref_clk disabled
[   15.563667] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: tx_lane0_sync_clk disabled
[   15.571143] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: rx_lane0_sync_clk disabled
[   15.579338] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: rx_lane1_sync_clk disabled
[   17.939055] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: core_clk enabled
[   17.939105] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: bus_aggr_clk enabled
[   17.946146] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: iface_clk enabled
[   17.953435] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: core_clk_unipro enabled
[   17.960861] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: core_clk_ice enabled
[   17.969103] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: ref_clk enabled
[   17.976821] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: tx_lane0_sync_clk enabled
[   17.984314] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: rx_lane0_sync_clk enabled
[   17.992406] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: rx_lane1_sync_clk enabled
[   18.075579] ufshcd-qcom 1da4000.ufshc: __ufshcd_uic_hibern8_enter: Hibern8 Enter at 18075560 us
[   18.075637] ufshcd-qcom 1da4000.ufshc: ufshcd_set_clk_freq: clk: core_clk, rate: 50000000
[   18.083140] ufshcd-qcom 1da4000.ufshc: ufshcd_set_clk_freq: clk: bus_aggr_clk, rate: 50000000
[   18.091486] ufshcd-qcom 1da4000.ufshc: ufshcd_set_clk_freq: clk: iface_clk, rate: 0
[   18.099936] ufshcd-qcom 1da4000.ufshc: ufshcd_set_clk_freq: clk: core_clk_unipro, rate: 37500000
[   18.107463] ufshcd-qcom 1da4000.ufshc: ufshcd_set_clk_freq: clk: core_clk_ice, rate: 75000000
[   18.116439] ufshcd-qcom 1da4000.ufshc: ufshcd_set_clk_freq: clk: ref_clk, rate: 1000
[   18.124859] ufshcd-qcom 1da4000.ufshc: ufshcd_set_clk_freq: clk: tx_lane0_sync_clk, rate: 0
[   18.132665] ufshcd-qcom 1da4000.ufshc: ufshcd_set_clk_freq: clk: rx_lane0_sync_clk, rate: 0
[   18.140928] ufshcd-qcom 1da4000.ufshc: ufshcd_set_clk_freq: clk: rx_lane1_sync_clk, rate: 0
[   18.152292] ufshcd-qcom 1da4000.ufshc: ufshcd_uic_hibern8_exit: Hibern8 Exit at 18152274 us
[   18.168689] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: core_clk disabled
[   18.168743] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: bus_aggr_clk disabled
[   18.175526] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: iface_clk disabled
[   18.184057] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: core_clk_unipro disabled
[   18.190639] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: core_clk_ice disabled
[   18.198949] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: ref_clk disabled
[   18.206797] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: tx_lane0_sync_clk disabled
[   18.214324] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: rx_lane0_sync_clk disabled
[   18.222492] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: rx_lane1_sync_clk disabled
[   18.868493] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: core_clk enabled
[   18.868543] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: bus_aggr_clk enabled
[   18.875510] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: iface_clk enabled
[   18.883318] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: core_clk_unipro enabled
[   18.890270] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: core_clk_ice enabled
[   18.898541] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: ref_clk enabled
[   18.906244] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: tx_lane0_sync_clk enabled
[   18.913690] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: rx_lane0_sync_clk enabled
[   18.921923] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: rx_lane1_sync_clk enabled
[   18.931224] ufshcd_wait_for_dev_cmd: time_left=150
[   18.938236] ufshcd_wait_for_dev_cmd = 0
[   18.945163] ufshcd-qcom 1da4000.ufshc: __ufshcd_uic_hibern8_enter: Hibern8 Enter at 18945144 us
[   18.949218] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: core_clk disabled
[   18.955483] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: bus_aggr_clk disabled
[   18.963097] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: iface_clk disabled
[   18.970992] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: core_clk_unipro disabled
[   18.978531] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: core_clk_ice disabled
[   18.986876] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: ref_clk disabled
[   18.995192] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: tx_lane0_sync_clk disabled
[   19.002740] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: rx_lane0_sync_clk disabled
[   19.010895] ufshcd-qcom 1da4000.ufshc: ufshcd_setup_clocks: clk: rx_lane1_sync_clk disabled
Jeffrey Hugo - Dec. 4, 2018, 4:35 p.m.
On 12/4/2018 9:17 AM, Marc Gonzalez wrote:

> 
> I booted a downstream kernel with UFS debug enabled (log provided below)
> 
> The one difference that jumps out at me is:
> 
> DOWNSTREAM
> [   10.902119] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: core_clk_unipro, rate: 150000000
> [   10.902161] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: core_clk_ice, rate: 300000000
> [   10.902198] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: ref_clk, rate: 1000
> 
> UPSTREAM
> [    2.072820] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: core_clk_unipro, rate: 0
> [    2.080304] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: core_clk_ice, rate: 0
> [    2.088547] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: ref_clk, rate: 0
> 
> 
> Jeffrey, I will check the regulators per your suggestion.
> I'm all ears if you have suggestions for the clocks as well.
> 

Hmm, this is interesting.

I know you mentioned before that the clock rates were 0.  Even with the 
downstream kernel, I've seen clock rates be zero (for other usecases).

Since we have a delta between downstream and upstream, that seems 
significant.

When I've seen a clock keep its rate 0 like this, its been because of a 
bad parent.  You can check this in upstream via debugfs - 
<debugfs>/clk/clk_summary
In downstream, I recall having to go into the individual clock sub 
directory, and reading the parent file.

However, maybe a simple solution.  Do you have 
https://patchwork.codeaurora.org/patch/657871/ ?
Marc Gonzalez - Dec. 4, 2018, 5:03 p.m.
On 04/12/2018 17:35, Jeffrey Hugo wrote:

> On 12/4/2018 9:17 AM, Marc Gonzalez wrote:
> 
>> I booted a downstream kernel with UFS debug enabled (log provided below)
>>
>> The one difference that jumps out at me is:
>>
>> DOWNSTREAM
>> [   10.902119] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: core_clk_unipro, rate: 150000000
>> [   10.902161] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: core_clk_ice, rate: 300000000
>> [   10.902198] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: ref_clk, rate: 1000
>>
>> UPSTREAM
>> [    2.072820] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: core_clk_unipro, rate: 0
>> [    2.080304] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: core_clk_ice, rate: 0
>> [    2.088547] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: ref_clk, rate: 0
>>
>>
>> Jeffrey, I will check the regulators per your suggestion.
>> I'm all ears if you have suggestions for the clocks as well.
> 
> Hmm, this is interesting.
> 
> I know you mentioned before that the clock rates were 0.  Even with the 
> downstream kernel, I've seen clock rates be zero (for other use-cases).
> 
> Since we have a delta between downstream and upstream, that seems 
> significant.
> 
> When I've seen a clock keep its rate 0 like this, its been because of a 
> bad parent.  You can check this in upstream via debugfs - 
> <debugfs>/clk/clk_summary
> In downstream, I recall having to go into the individual clock sub 
> directory, and reading the parent file.
> 
> However, maybe a simple solution.  Do you have 
> https://patchwork.codeaurora.org/patch/657871/ ?

Yep!

$ git show --pretty=fuller 79bf268a13bf
commit 79bf268a13bf24e46db54fd836807fdfccaf7d59
Author:     Jeffrey Hugo <jhugo@codeaurora.org>
AuthorDate: Thu Nov 15 13:44:53 2018 -0700
Commit:     Marc Gonzalez <marc.w.gonzalez@free.fr>
CommitDate: Thu Nov 29 10:03:33 2018 +0100

    arm64: dts: qcom: msm8998: correct xo clock name


Not sure I have the clk debug config knob, /sys/kernel/debug is empty.
I'm off to tweak :-)

Regards.
Jeffrey Hugo - Dec. 4, 2018, 5:05 p.m.
On 12/4/2018 10:03 AM, Marc Gonzalez wrote:
> On 04/12/2018 17:35, Jeffrey Hugo wrote:
> 
>> On 12/4/2018 9:17 AM, Marc Gonzalez wrote:
>>
>>> I booted a downstream kernel with UFS debug enabled (log provided below)
>>>
>>> The one difference that jumps out at me is:
>>>
>>> DOWNSTREAM
>>> [   10.902119] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: core_clk_unipro, rate: 150000000
>>> [   10.902161] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: core_clk_ice, rate: 300000000
>>> [   10.902198] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: ref_clk, rate: 1000
>>>
>>> UPSTREAM
>>> [    2.072820] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: core_clk_unipro, rate: 0
>>> [    2.080304] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: core_clk_ice, rate: 0
>>> [    2.088547] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: ref_clk, rate: 0
>>>
>>>
>>> Jeffrey, I will check the regulators per your suggestion.
>>> I'm all ears if you have suggestions for the clocks as well.
>>
>> Hmm, this is interesting.
>>
>> I know you mentioned before that the clock rates were 0.  Even with the
>> downstream kernel, I've seen clock rates be zero (for other use-cases).
>>
>> Since we have a delta between downstream and upstream, that seems
>> significant.
>>
>> When I've seen a clock keep its rate 0 like this, its been because of a
>> bad parent.  You can check this in upstream via debugfs -
>> <debugfs>/clk/clk_summary
>> In downstream, I recall having to go into the individual clock sub
>> directory, and reading the parent file.
>>
>> However, maybe a simple solution.  Do you have
>> https://patchwork.codeaurora.org/patch/657871/ ?
> 
> Yep!
> 
> $ git show --pretty=fuller 79bf268a13bf
> commit 79bf268a13bf24e46db54fd836807fdfccaf7d59
> Author:     Jeffrey Hugo <jhugo@codeaurora.org>
> AuthorDate: Thu Nov 15 13:44:53 2018 -0700
> Commit:     Marc Gonzalez <marc.w.gonzalez@free.fr>
> CommitDate: Thu Nov 29 10:03:33 2018 +0100
> 
>      arm64: dts: qcom: msm8998: correct xo clock name
> 
> 
> Not sure I have the clk debug config knob, /sys/kernel/debug is empty.
> I'm off to tweak :-)

mount -t debugfs none /sys/kernel/debug
Marc Gonzalez - Dec. 4, 2018, 5:11 p.m.
On 04/12/2018 18:05, Jeffrey Hugo wrote:

> mount -t debugfs none /sys/kernel/debug

Doh!

# cat /sys/kernel/debug/clk/clk_summary 
                                 enable  prepare  protect                                duty
   clock                          count    count    count        rate   accuracy phase  cycle
---------------------------------------------------------------------------------------------
 gcc_usb_phy_cfg_ahb2phy_clk          0        0        0           0          0     0  50000
 gcc_usb3_phy_pipe_clk                0        0        0           0          0     0  50000
 gcc_usb30_sleep_clk                  0        0        0           0          0     0  50000
 gcc_ufs_unipro_core_clk              0        0        0           0          0     0  50000
 gcc_ufs_tx_symbol_0_clk              0        0        0           0          0     0  50000
 gcc_ufs_rx_symbol_1_clk              0        0        0           0          0     0  50000
 gcc_ufs_rx_symbol_0_clk              0        0        0           0          0     0  50000
 gcc_ufs_phy_aux_clk                  0        0        0           0          0     0  50000
 gcc_ufs_ice_core_clk                 0        0        0           0          0     0  50000
 gcc_ufs_ahb_clk                      0        0        0           0          0     0  50000
 gcc_tsif_inactivity_timers_clk       0        0        0           0          0     0  50000
 gcc_tsif_ahb_clk                     0        0        0           0          0     0  50000
 gcc_sdcc4_ahb_clk                    0        0        0           0          0     0  50000
 gcc_sdcc2_ahb_clk                    0        0        0           0          0     0  50000
 gcc_prng_ahb_clk                     0        0        0           0          0     0  50000
 gcc_pdm_xo4_clk                      0        0        0           0          0     0  50000
 gcc_pdm_ahb_clk                      0        0        0           0          0     0  50000
 gcc_pcie_0_slv_axi_clk               0        0        0           0          0     0  50000
 gcc_pcie_0_pipe_clk                  0        0        0           0          0     0  50000
 gcc_pcie_0_mstr_axi_clk              0        0        0           0          0     0  50000
 gcc_pcie_0_cfg_ahb_clk               0        0        0           0          0     0  50000
 gcc_mss_at_clk                       0        0        0           0          0     0  50000
 gcc_mmss_sys_noc_axi_clk             0        0        0           0          0     0  50000
 gcc_mmss_qm_core_clk                 0        0        0           0          0     0  50000
 gcc_mmss_qm_ahb_clk                  0        0        0           0          0     0  50000
 gcc_mmss_noc_cfg_ahb_clk             0        0        0           0          0     0  50000
 gcc_lpass_trig_clk                   0        0        0           0          0     0  50000
 gcc_lpass_at_clk                     1        1        0           0          0     0  50000
 gcc_hmss_trig_clk                    0        0        0           0          0     0  50000
 gcc_hmss_dvm_bus_clk                 1        1        0           0          0     0  50000
 gcc_hmss_at_clk                      0        0        0           0          0     0  50000
 gcc_gpu_snoc_dvm_gfx_clk             0        0        0           0          0     0  50000
 gcc_gpu_cfg_ahb_clk                  0        0        0           0          0     0  50000
 gcc_gpu_bimc_gfx_src_clk             0        0        0           0          0     0  50000
 gcc_gpu_bimc_gfx_clk                 0        0        0           0          0     0  50000
 gcc_blsp2_sleep_clk                  0        0        0           0          0     0  50000
 gcc_blsp2_ahb_clk                    3        3        0           0          0     0  50000
 gcc_blsp1_sleep_clk                  0        0        0           0          0     0  50000
 gcc_blsp1_ahb_clk                    0        0        0           0          0     0  50000
 gcc_bimc_mss_q6_axi_clk              0        0        0           0          0     0  50000
 gcc_bimc_hmss_axi_clk                0        0        0           0          0     0  50000
 gcc_apss_qdss_tsctr_div8_clk         0        0        0           0          0     0  50000
 gcc_apss_qdss_tsctr_div2_clk         0        0        0           0          0     0  50000
 gcc_aggre1_noc_xo_clk                0        0        0           0          0     0  50000
 sleep_clk                            0        0        0       32764          0     0  50000
 xo                                   1        1        0    19200000          0     0  50000
    gcc_rx1_usb2_clkref_clk           0        0        0    19200000          0     0  50000
    gcc_pcie_clkref_clk               0        0        0    19200000          0     0  50000
    gcc_ufs_clkref_clk                0        0        0    19200000          0     0  50000
    gcc_hdmi_clkref_clk               0        0        0    19200000          0     0  50000
    gcc_usb3_clkref_clk               0        0        0    19200000          0     0  50000
    usb3_phy_aux_clk_src              0        0        0     1200000          0     0  50000
       gcc_usb3_phy_aux_clk           0        0        0     1200000          0     0  50000
    usb30_mock_utmi_clk_src           0        0        0    19200000          0     0  50000
       gcc_usb30_mock_utmi_clk        0        0        0    19200000          0     0  50000
    tsif_ref_clk_src                  0        0        0    19200000          0     0  50000
       gcc_tsif_ref_clk               0        0        0    19200000          0     0  50000
    sdcc4_apps_clk_src                0        0        0    19200000          0     0  50000
       gcc_sdcc4_apps_clk             0        0        0    19200000          0     0  50000
    sdcc2_apps_clk_src                0        0        0    19200000          0     0  50000
       gcc_sdcc2_apps_clk             0        0        0    19200000          0     0  50000
    pdm2_clk_src                      0        0        0    19200000          0     0  50000
       gcc_pdm2_clk                   0        0        0    19200000          0     0  50000
    pcie_aux_clk_src                  0        0        0    19200000          0     0  50000
       gcc_pcie_0_aux_clk             0        0        0    19200000          0     0  50000
       gcc_pcie_phy_aux_clk           0        0        0    19200000          0     0  50000
    hmss_rbcpr_clk_src                0        0        0    19200000          0     0  50000
       gcc_hmss_rbcpr_clk             0        0        0    19200000          0     0  50000
    hmss_ahb_clk_src                  0        0        0    19200000          0     0  50000
       gcc_hmss_ahb_clk               0        0        0    19200000          0     0  50000
    gpll4                             0        0        0   384000000          0     0  50000
       gpll4_out_test                 0        0        0   384000000          0     0  50000
       gpll4_out_odd                  0        0        0   384000000          0     0  50000
       gpll4_out_main                 0        0        0   384000000          0     0  50000
       gpll4_out_even                 0        0        0   384000000          0     0  50000
    gpll3                             0        0        0   921600000          0     0  50000
       gpll3_out_test                 0        0        0   921600000          0     0  50000
       gpll3_out_odd                  0        0        0   921600000          0     0  50000
       gpll3_out_main                 0        0        0   921600000          0     0  50000
       gpll3_out_even                 0        0        0   921600000          0     0  50000
    gpll2                             0        0        0  1286400000          0     0  50000
       gpll2_out_test                 0        0        0  1286400000          0     0  50000
       gpll2_out_odd                  0        0        0  1286400000          0     0  50000
       gpll2_out_main                 0        0        0  1286400000          0     0  50000
       gpll2_out_even                 0        0        0  1286400000          0     0  50000
    gpll1                             0        0        0  1056000000          0     0  50000
       gpll1_out_test                 0        0        0  1056000000          0     0  50000
       gpll1_out_odd                  0        0        0  1056000000          0     0  50000
       gpll1_out_main                 0        0        0  1056000000          0     0  50000
       gpll1_out_even                 0        0        0  1056000000          0     0  50000
    gpll0                             0        0        0   595200000          0     0  50000
       gpll0_out_test                 0        0        0   595200000          0     0  50000
       gpll0_out_odd                  0        0        0   595200000          0     0  50000
       gpll0_out_main                 0        0        0   595200000          0     0  50000
          usb30_master_clk_src        0        0        0   119040000          0     0  50000
             gcc_aggre1_usb3_axi_clk       0        0        0   119040000          0     0  50000
             gcc_cfg_noc_usb3_axi_clk       0        0        0   119040000          0     0  50000
             gcc_usb30_master_clk       0        0        0   119040000          0     0  50000
          ufs_axi_clk_src             0        0        0   198400000          0     0  50000
             gcc_aggre1_ufs_axi_clk       0        0        0   198400000          0     0  50000
             gcc_ufs_axi_clk          0        0        0   198400000          0     0  50000
       gpll0_out_even                 0        0        0   595200000          0     0  50000
    gp3_clk_src                       0        0        0    19200000          0     0  50000
       gcc_gp3_clk                    0        0        0    19200000          0     0  50000
    gp2_clk_src                       0        0        0    19200000          0     0  50000
       gcc_gp2_clk                    0        0        0    19200000          0     0  50000
    gp1_clk_src                       0        0        0    19200000          0     0  50000
       gcc_gp1_clk                    0        0        0    19200000          0     0  50000
    blsp2_uart3_apps_clk_src          0        0        0    19200000          0     0  50000
       gcc_blsp2_uart3_apps_clk       0        0        0    19200000          0     0  50000
    blsp2_uart2_apps_clk_src          1        1        0     1843200          0     0  50000
       gcc_blsp2_uart2_apps_clk       3        3        0     1843200          0     0  50000
    blsp2_uart1_apps_clk_src          0        0        0    19200000          0     0  50000
       gcc_blsp2_uart1_apps_clk       0        0        0    19200000          0     0  50000
    blsp2_qup6_spi_apps_clk_src       0        0        0    19200000          0     0  50000
       gcc_blsp2_qup6_spi_apps_clk       0        0        0    19200000          0     0  50000
    blsp2_qup6_i2c_apps_clk_src       0        0        0    19200000          0     0  50000
       gcc_blsp2_qup6_i2c_apps_clk       0        0        0    19200000          0     0  50000
    blsp2_qup5_spi_apps_clk_src       0        0        0    19200000          0     0  50000
       gcc_blsp2_qup5_spi_apps_clk       0        0        0    19200000          0     0  50000
    blsp2_qup5_i2c_apps_clk_src       0        0        0    19200000          0     0  50000
       gcc_blsp2_qup5_i2c_apps_clk       0        0        0    19200000          0     0  50000
    blsp2_qup4_spi_apps_clk_src       0        0        0    19200000          0     0  50000
       gcc_blsp2_qup4_spi_apps_clk       0        0        0    19200000          0     0  50000
    blsp2_qup4_i2c_apps_clk_src       0        0        0    19200000          0     0  50000
       gcc_blsp2_qup4_i2c_apps_clk       0        0        0    19200000          0     0  50000
    blsp2_qup3_spi_apps_clk_src       0        0        0    19200000          0     0  50000
       gcc_blsp2_qup3_spi_apps_clk       0        0        0    19200000          0     0  50000
    blsp2_qup3_i2c_apps_clk_src       0        0        0    19200000          0     0  50000
       gcc_blsp2_qup3_i2c_apps_clk       0        0        0    19200000          0     0  50000
    blsp2_qup2_spi_apps_clk_src       0        0        0    19200000          0     0  50000
       gcc_blsp2_qup2_spi_apps_clk       0        0        0    19200000          0     0  50000
    blsp2_qup2_i2c_apps_clk_src       0        0        0    19200000          0     0  50000
       gcc_blsp2_qup2_i2c_apps_clk       0        0        0    19200000          0     0  50000
    blsp2_qup1_spi_apps_clk_src       0        0        0    19200000          0     0  50000
       gcc_blsp2_qup1_spi_apps_clk       0        0        0    19200000          0     0  50000
    blsp2_qup1_i2c_apps_clk_src       0        0        0    19200000          0     0  50000
       gcc_blsp2_qup1_i2c_apps_clk       0        0        0    19200000          0     0  50000
    blsp1_uart3_apps_clk_src          0        0        0    19200000          0     0  50000
       gcc_blsp1_uart3_apps_clk       0        0        0    19200000          0     0  50000
    blsp1_uart2_apps_clk_src          0        0        0    19200000          0     0  50000
       gcc_blsp1_uart2_apps_clk       0        0        0    19200000          0     0  50000
    blsp1_uart1_apps_clk_src          0        0        0    19200000          0     0  50000
       gcc_blsp1_uart1_apps_clk       0        0        0    19200000          0     0  50000
    blsp1_qup6_spi_apps_clk_src       0        0        0    19200000          0     0  50000
       gcc_blsp1_qup6_spi_apps_clk       0        0        0    19200000          0     0  50000
    blsp1_qup6_i2c_apps_clk_src       0        0        0    19200000          0     0  50000
       gcc_blsp1_qup6_i2c_apps_clk       0        0        0    19200000          0     0  50000
    blsp1_qup5_spi_apps_clk_src       0        0        0    19200000          0     0  50000
       gcc_blsp1_qup5_spi_apps_clk       0        0        0    19200000          0     0  50000
    blsp1_qup5_i2c_apps_clk_src       0        0        0    19200000          0     0  50000
       gcc_blsp1_qup5_i2c_apps_clk       0        0        0    19200000          0     0  50000
    blsp1_qup4_spi_apps_clk_src       0        0        0    19200000          0     0  50000
       gcc_blsp1_qup4_spi_apps_clk       0        0        0    19200000          0     0  50000
    blsp1_qup4_i2c_apps_clk_src       0        0        0    19200000          0     0  50000
       gcc_blsp1_qup4_i2c_apps_clk       0        0        0    19200000          0     0  50000
    blsp1_qup3_spi_apps_clk_src       0        0        0    19200000          0     0  50000
       gcc_blsp1_qup3_spi_apps_clk       0        0        0    19200000          0     0  50000
    blsp1_qup3_i2c_apps_clk_src       0        0        0    19200000          0     0  50000
       gcc_blsp1_qup3_i2c_apps_clk       0        0        0    19200000          0     0  50000
    blsp1_qup2_spi_apps_clk_src       0        0        0    19200000          0     0  50000
       gcc_blsp1_qup2_spi_apps_clk       0        0        0    19200000          0     0  50000
    blsp1_qup2_i2c_apps_clk_src       0        0        0    19200000          0     0  50000
       gcc_blsp1_qup2_i2c_apps_clk       0        0        0    19200000          0     0  50000
    blsp1_qup1_spi_apps_clk_src       0        0        0    19200000          0     0  50000
       gcc_blsp1_qup1_spi_apps_clk       0        0        0    19200000          0     0  50000
    blsp1_qup1_i2c_apps_clk_src       0        0        0    19200000          0     0  50000
       gcc_blsp1_qup1_i2c_apps_clk       0        0        0    19200000          0     0  50000
 ln_bb_a_clk1                         0        0        0           0          0     0  50000
 ln_bb_clk1                           0        0        0           0          0     0  50000


There is no clock summary in 4.4 to compare the downstream kernel?

Regards.
Jeffrey Hugo - Dec. 4, 2018, 5:21 p.m.
On 12/4/2018 10:11 AM, Marc Gonzalez wrote:
> On 04/12/2018 18:05, Jeffrey Hugo wrote:
> 
>> mount -t debugfs none /sys/kernel/debug
> 
> Doh!
> 
> # cat /sys/kernel/debug/clk/clk_summary
>                                   enable  prepare  protect                                duty
>     clock                          count    count    count        rate   accuracy phase  cycle
> ---------------------------------------------------------------------------------------------
>   gcc_usb_phy_cfg_ahb2phy_clk          0        0        0           0          0     0  50000
>   gcc_usb3_phy_pipe_clk                0        0        0           0          0     0  50000
>   gcc_usb30_sleep_clk                  0        0        0           0          0     0  50000
>   gcc_ufs_unipro_core_clk              0        0        0           0          0     0  50000

Yeah, this clock has no parent, and is one of the ones that is a delta 
from the downsteam per your logs.

>   gcc_ufs_tx_symbol_0_clk              0        0        0           0          0     0  50000
>   gcc_ufs_rx_symbol_1_clk              0        0        0           0          0     0  50000
>   gcc_ufs_rx_symbol_0_clk              0        0        0           0          0     0  50000
>   gcc_ufs_phy_aux_clk                  0        0        0           0          0     0  50000
>   gcc_ufs_ice_core_clk                 0        0        0           0          0     0  50000
>   gcc_ufs_ahb_clk                      0        0        0           0          0     0  50000
>   gcc_tsif_inactivity_timers_clk       0        0        0           0          0     0  50000
>   gcc_tsif_ahb_clk                     0        0        0           0          0     0  50000
>   gcc_sdcc4_ahb_clk                    0        0        0           0          0     0  50000
>   gcc_sdcc2_ahb_clk                    0        0        0           0          0     0  50000
>   gcc_prng_ahb_clk                     0        0        0           0          0     0  50000
>   gcc_pdm_xo4_clk                      0        0        0           0          0     0  50000
>   gcc_pdm_ahb_clk                      0        0        0           0          0     0  50000
>   gcc_pcie_0_slv_axi_clk               0        0        0           0          0     0  50000
>   gcc_pcie_0_pipe_clk                  0        0        0           0          0     0  50000
>   gcc_pcie_0_mstr_axi_clk              0        0        0           0          0     0  50000
>   gcc_pcie_0_cfg_ahb_clk               0        0        0           0          0     0  50000
>   gcc_mss_at_clk                       0        0        0           0          0     0  50000
>   gcc_mmss_sys_noc_axi_clk             0        0        0           0          0     0  50000
>   gcc_mmss_qm_core_clk                 0        0        0           0          0     0  50000
>   gcc_mmss_qm_ahb_clk                  0        0        0           0          0     0  50000
>   gcc_mmss_noc_cfg_ahb_clk             0        0        0           0          0     0  50000
>   gcc_lpass_trig_clk                   0        0        0           0          0     0  50000
>   gcc_lpass_at_clk                     1        1        0           0          0     0  50000
>   gcc_hmss_trig_clk                    0        0        0           0          0     0  50000
>   gcc_hmss_dvm_bus_clk                 1        1        0           0          0     0  50000
>   gcc_hmss_at_clk                      0        0        0           0          0     0  50000
>   gcc_gpu_snoc_dvm_gfx_clk             0        0        0           0          0     0  50000
>   gcc_gpu_cfg_ahb_clk                  0        0        0           0          0     0  50000
>   gcc_gpu_bimc_gfx_src_clk             0        0        0           0          0     0  50000
>   gcc_gpu_bimc_gfx_clk                 0        0        0           0          0     0  50000
>   gcc_blsp2_sleep_clk                  0        0        0           0          0     0  50000
>   gcc_blsp2_ahb_clk                    3        3        0           0          0     0  50000
>   gcc_blsp1_sleep_clk                  0        0        0           0          0     0  50000
>   gcc_blsp1_ahb_clk                    0        0        0           0          0     0  50000
>   gcc_bimc_mss_q6_axi_clk              0        0        0           0          0     0  50000
>   gcc_bimc_hmss_axi_clk                0        0        0           0          0     0  50000
>   gcc_apss_qdss_tsctr_div8_clk         0        0        0           0          0     0  50000
>   gcc_apss_qdss_tsctr_div2_clk         0        0        0           0          0     0  50000
>   gcc_aggre1_noc_xo_clk                0        0        0           0          0     0  50000
>   sleep_clk                            0        0        0       32764          0     0  50000
>   xo                                   1        1        0    19200000          0     0  50000
>      gcc_rx1_usb2_clkref_clk           0        0        0    19200000          0     0  50000
>      gcc_pcie_clkref_clk               0        0        0    19200000          0     0  50000
>      gcc_ufs_clkref_clk                0        0        0    19200000          0     0  50000
>      gcc_hdmi_clkref_clk               0        0        0    19200000          0     0  50000
>      gcc_usb3_clkref_clk               0        0        0    19200000          0     0  50000
>      usb3_phy_aux_clk_src              0        0        0     1200000          0     0  50000
>         gcc_usb3_phy_aux_clk           0        0        0     1200000          0     0  50000
>      usb30_mock_utmi_clk_src           0        0        0    19200000          0     0  50000
>         gcc_usb30_mock_utmi_clk        0        0        0    19200000          0     0  50000
>      tsif_ref_clk_src                  0        0        0    19200000          0     0  50000
>         gcc_tsif_ref_clk               0        0        0    19200000          0     0  50000
>      sdcc4_apps_clk_src                0        0        0    19200000          0     0  50000
>         gcc_sdcc4_apps_clk             0        0        0    19200000          0     0  50000
>      sdcc2_apps_clk_src                0        0        0    19200000          0     0  50000
>         gcc_sdcc2_apps_clk             0        0        0    19200000          0     0  50000
>      pdm2_clk_src                      0        0        0    19200000          0     0  50000
>         gcc_pdm2_clk                   0        0        0    19200000          0     0  50000
>      pcie_aux_clk_src                  0        0        0    19200000          0     0  50000
>         gcc_pcie_0_aux_clk             0        0        0    19200000          0     0  50000
>         gcc_pcie_phy_aux_clk           0        0        0    19200000          0     0  50000
>      hmss_rbcpr_clk_src                0        0        0    19200000          0     0  50000
>         gcc_hmss_rbcpr_clk             0        0        0    19200000          0     0  50000
>      hmss_ahb_clk_src                  0        0        0    19200000          0     0  50000
>         gcc_hmss_ahb_clk               0        0        0    19200000          0     0  50000
>      gpll4                             0        0        0   384000000          0     0  50000
>         gpll4_out_test                 0        0        0   384000000          0     0  50000
>         gpll4_out_odd                  0        0        0   384000000          0     0  50000
>         gpll4_out_main                 0        0        0   384000000          0     0  50000
>         gpll4_out_even                 0        0        0   384000000          0     0  50000
>      gpll3                             0        0        0   921600000          0     0  50000
>         gpll3_out_test                 0        0        0   921600000          0     0  50000
>         gpll3_out_odd                  0        0        0   921600000          0     0  50000
>         gpll3_out_main                 0        0        0   921600000          0     0  50000
>         gpll3_out_even                 0        0        0   921600000          0     0  50000
>      gpll2                             0        0        0  1286400000          0     0  50000
>         gpll2_out_test                 0        0        0  1286400000          0     0  50000
>         gpll2_out_odd                  0        0        0  1286400000          0     0  50000
>         gpll2_out_main                 0        0        0  1286400000          0     0  50000
>         gpll2_out_even                 0        0        0  1286400000          0     0  50000
>      gpll1                             0        0        0  1056000000          0     0  50000
>         gpll1_out_test                 0        0        0  1056000000          0     0  50000
>         gpll1_out_odd                  0        0        0  1056000000          0     0  50000
>         gpll1_out_main                 0        0        0  1056000000          0     0  50000
>         gpll1_out_even                 0        0        0  1056000000          0     0  50000
>      gpll0                             0        0        0   595200000          0     0  50000
>         gpll0_out_test                 0        0        0   595200000          0     0  50000
>         gpll0_out_odd                  0        0        0   595200000          0     0  50000
>         gpll0_out_main                 0        0        0   595200000          0     0  50000
>            usb30_master_clk_src        0        0        0   119040000          0     0  50000
>               gcc_aggre1_usb3_axi_clk       0        0        0   119040000          0     0  50000
>               gcc_cfg_noc_usb3_axi_clk       0        0        0   119040000          0     0  50000
>               gcc_usb30_master_clk       0        0        0   119040000          0     0  50000
>            ufs_axi_clk_src             0        0        0   198400000          0     0  50000
>               gcc_aggre1_ufs_axi_clk       0        0        0   198400000          0     0  50000
>               gcc_ufs_axi_clk          0        0        0   198400000          0     0  50000
>         gpll0_out_even                 0        0        0   595200000          0     0  50000
>      gp3_clk_src                       0        0        0    19200000          0     0  50000
>         gcc_gp3_clk                    0        0        0    19200000          0     0  50000
>      gp2_clk_src                       0        0        0    19200000          0     0  50000
>         gcc_gp2_clk                    0        0        0    19200000          0     0  50000
>      gp1_clk_src                       0        0        0    19200000          0     0  50000
>         gcc_gp1_clk                    0        0        0    19200000          0     0  50000
>      blsp2_uart3_apps_clk_src          0        0        0    19200000          0     0  50000
>         gcc_blsp2_uart3_apps_clk       0        0        0    19200000          0     0  50000
>      blsp2_uart2_apps_clk_src          1        1        0     1843200          0     0  50000
>         gcc_blsp2_uart2_apps_clk       3        3        0     1843200          0     0  50000
>      blsp2_uart1_apps_clk_src          0        0        0    19200000          0     0  50000
>         gcc_blsp2_uart1_apps_clk       0        0        0    19200000          0     0  50000
>      blsp2_qup6_spi_apps_clk_src       0        0        0    19200000          0     0  50000
>         gcc_blsp2_qup6_spi_apps_clk       0        0        0    19200000          0     0  50000
>      blsp2_qup6_i2c_apps_clk_src       0        0        0    19200000          0     0  50000
>         gcc_blsp2_qup6_i2c_apps_clk       0        0        0    19200000          0     0  50000
>      blsp2_qup5_spi_apps_clk_src       0        0        0    19200000          0     0  50000
>         gcc_blsp2_qup5_spi_apps_clk       0        0        0    19200000          0     0  50000
>      blsp2_qup5_i2c_apps_clk_src       0        0        0    19200000          0     0  50000
>         gcc_blsp2_qup5_i2c_apps_clk       0        0        0    19200000          0     0  50000
>      blsp2_qup4_spi_apps_clk_src       0        0        0    19200000          0     0  50000
>         gcc_blsp2_qup4_spi_apps_clk       0        0        0    19200000          0     0  50000
>      blsp2_qup4_i2c_apps_clk_src       0        0        0    19200000          0     0  50000
>         gcc_blsp2_qup4_i2c_apps_clk       0        0        0    19200000          0     0  50000
>      blsp2_qup3_spi_apps_clk_src       0        0        0    19200000          0     0  50000
>         gcc_blsp2_qup3_spi_apps_clk       0        0        0    19200000          0     0  50000
>      blsp2_qup3_i2c_apps_clk_src       0        0        0    19200000          0     0  50000
>         gcc_blsp2_qup3_i2c_apps_clk       0        0        0    19200000          0     0  50000
>      blsp2_qup2_spi_apps_clk_src       0        0        0    19200000          0     0  50000
>         gcc_blsp2_qup2_spi_apps_clk       0        0        0    19200000          0     0  50000
>      blsp2_qup2_i2c_apps_clk_src       0        0        0    19200000          0     0  50000
>         gcc_blsp2_qup2_i2c_apps_clk       0        0        0    19200000          0     0  50000
>      blsp2_qup1_spi_apps_clk_src       0        0        0    19200000          0     0  50000
>         gcc_blsp2_qup1_spi_apps_clk       0        0        0    19200000          0     0  50000
>      blsp2_qup1_i2c_apps_clk_src       0        0        0    19200000          0     0  50000
>         gcc_blsp2_qup1_i2c_apps_clk       0        0        0    19200000          0     0  50000
>      blsp1_uart3_apps_clk_src          0        0        0    19200000          0     0  50000
>         gcc_blsp1_uart3_apps_clk       0        0        0    19200000          0     0  50000
>      blsp1_uart2_apps_clk_src          0        0        0    19200000          0     0  50000
>         gcc_blsp1_uart2_apps_clk       0        0        0    19200000          0     0  50000
>      blsp1_uart1_apps_clk_src          0        0        0    19200000          0     0  50000
>         gcc_blsp1_uart1_apps_clk       0        0        0    19200000          0     0  50000
>      blsp1_qup6_spi_apps_clk_src       0        0        0    19200000          0     0  50000
>         gcc_blsp1_qup6_spi_apps_clk       0        0        0    19200000          0     0  50000
>      blsp1_qup6_i2c_apps_clk_src       0        0        0    19200000          0     0  50000
>         gcc_blsp1_qup6_i2c_apps_clk       0        0        0    19200000          0     0  50000
>      blsp1_qup5_spi_apps_clk_src       0        0        0    19200000          0     0  50000
>         gcc_blsp1_qup5_spi_apps_clk       0        0        0    19200000          0     0  50000
>      blsp1_qup5_i2c_apps_clk_src       0        0        0    19200000          0     0  50000
>         gcc_blsp1_qup5_i2c_apps_clk       0        0        0    19200000          0     0  50000
>      blsp1_qup4_spi_apps_clk_src       0        0        0    19200000          0     0  50000
>         gcc_blsp1_qup4_spi_apps_clk       0        0        0    19200000          0     0  50000
>      blsp1_qup4_i2c_apps_clk_src       0        0        0    19200000          0     0  50000
>         gcc_blsp1_qup4_i2c_apps_clk       0        0        0    19200000          0     0  50000
>      blsp1_qup3_spi_apps_clk_src       0        0        0    19200000          0     0  50000
>         gcc_blsp1_qup3_spi_apps_clk       0        0        0    19200000          0     0  50000
>      blsp1_qup3_i2c_apps_clk_src       0        0        0    19200000          0     0  50000
>         gcc_blsp1_qup3_i2c_apps_clk       0        0        0    19200000          0     0  50000
>      blsp1_qup2_spi_apps_clk_src       0        0        0    19200000          0     0  50000
>         gcc_blsp1_qup2_spi_apps_clk       0        0        0    19200000          0     0  50000
>      blsp1_qup2_i2c_apps_clk_src       0        0        0    19200000          0     0  50000
>         gcc_blsp1_qup2_i2c_apps_clk       0        0        0    19200000          0     0  50000
>      blsp1_qup1_spi_apps_clk_src       0        0        0    19200000          0     0  50000
>         gcc_blsp1_qup1_spi_apps_clk       0        0        0    19200000          0     0  50000
>      blsp1_qup1_i2c_apps_clk_src       0        0        0    19200000          0     0  50000
>         gcc_blsp1_qup1_i2c_apps_clk       0        0        0    19200000          0     0  50000
>   ln_bb_a_clk1                         0        0        0           0          0     0  50000
>   ln_bb_clk1                           0        0        0           0          0     0  50000
> 
> 
> There is no clock summary in 4.4 to compare the downstream kernel?

Not that I've seen.  You can check each clock individually, but I 
realize that is tedious.
Jeffrey Hugo - Dec. 4, 2018, 5:31 p.m.
On 12/4/2018 10:21 AM, Jeffrey Hugo wrote:
> On 12/4/2018 10:11 AM, Marc Gonzalez wrote:
>> On 04/12/2018 18:05, Jeffrey Hugo wrote:
>>
>>> mount -t debugfs none /sys/kernel/debug
>>
>> Doh!
>>
>> # cat /sys/kernel/debug/clk/clk_summary
>>                                   enable  prepare  
>> protect                                duty
>>     clock                          count    count    count        
>> rate   accuracy phase  cycle
>> --------------------------------------------------------------------------------------------- 
>>
>>   gcc_usb_phy_cfg_ahb2phy_clk          0        0        0           
>> 0          0     0  50000
>>   gcc_usb3_phy_pipe_clk                0        0        0           
>> 0          0     0  50000
>>   gcc_usb30_sleep_clk                  0        0        0           
>> 0          0     0  50000
>>   gcc_ufs_unipro_core_clk              0        0        0           
>> 0          0     0  50000
> 
> Yeah, this clock has no parent, and is one of the ones that is a delta 
> from the downsteam per your logs.

 From what I can tell from the documentation, this is sourced from 
ufs_unipro_core_clk_src, which is inturn sourced from gpll0_out_main. 
I'm guessing gcc-msm8998.c needs to be updated to reflect this.  It 
would also be good to check this against the downstream kernel.

Let me know if you want me to have a look at any other specific clocks.
Marc Gonzalez - Dec. 6, 2018, 4:15 p.m.
On 04/12/2018 18:31, Jeffrey Hugo wrote:

> From what I can tell from the documentation, this is sourced from 
> ufs_unipro_core_clk_src, which is inturn sourced from gpll0_out_main. 
> I'm guessing gcc-msm8998.c needs to be updated to reflect this.  It 
> would also be good to check this against the downstream kernel.

With Stephen's "define xo clock" patch applied:

# cat clk_summary
                                 enable  prepare  protect                                duty
   clock                          count    count    count        rate   accuracy phase  cycle
---------------------------------------------------------------------------------------------
 gcc_usb_phy_cfg_ahb2phy_clk          0        0        0           0          0     0  50000
 gcc_usb3_phy_pipe_clk                0        0        0           0          0     0  50000
 gcc_usb30_sleep_clk                  0        0        0           0          0     0  50000
 gcc_ufs_tx_symbol_0_clk              0        0        0           0          0     0  50000
 gcc_ufs_rx_symbol_1_clk              0        0        0           0          0     0  50000
 gcc_ufs_rx_symbol_0_clk              0        0        0           0          0     0  50000
 gcc_ufs_phy_aux_clk                  0        0        0           0          0     0  50000
 gcc_ufs_ice_core_clk                 0        0        0           0          0     0  50000
 gcc_ufs_ahb_clk                      0        0        0           0          0     0  50000
 gcc_tsif_inactivity_timers_clk       0        0        0           0          0     0  50000
 gcc_tsif_ahb_clk                     0        0        0           0          0     0  50000
 gcc_sdcc4_ahb_clk                    0        0        0           0          0     0  50000
 gcc_sdcc2_ahb_clk                    0        0        0           0          0     0  50000
 gcc_prng_ahb_clk                     0        0        0           0          0     0  50000
 gcc_pdm_xo4_clk                      0        0        0           0          0     0  50000
 gcc_pdm_ahb_clk                      0        0        0           0          0     0  50000
 gcc_pcie_0_slv_axi_clk               0        0        0           0          0     0  50000
 gcc_pcie_0_pipe_clk                  0        0        0           0          0     0  50000
 gcc_pcie_0_mstr_axi_clk              0        0        0           0          0     0  50000
 gcc_pcie_0_cfg_ahb_clk               0        0        0           0          0     0  50000
 gcc_mss_at_clk                       0        0        0           0          0     0  50000
 gcc_mmss_sys_noc_axi_clk             0        0        0           0          0     0  50000
 gcc_mmss_qm_core_clk                 0        0        0           0          0     0  50000
 gcc_mmss_qm_ahb_clk                  0        0        0           0          0     0  50000
 gcc_mmss_noc_cfg_ahb_clk             0        0        0           0          0     0  50000
 gcc_lpass_trig_clk                   0        0        0           0          0     0  50000
 gcc_lpass_at_clk                     1        1        0           0          0     0  50000
 gcc_hmss_trig_clk                    0        0        0           0          0     0  50000
 gcc_hmss_dvm_bus_clk                 1        1        0           0          0     0  50000
 gcc_hmss_at_clk                      0        0        0           0          0     0  50000
 gcc_gpu_snoc_dvm_gfx_clk             0        0        0           0          0     0  50000
 gcc_gpu_cfg_ahb_clk                  0        0        0           0          0     0  50000
 gcc_gpu_bimc_gfx_src_clk             0        0        0           0          0     0  50000
 gcc_gpu_bimc_gfx_clk                 0        0        0           0          0     0  50000
 gcc_blsp2_sleep_clk                  0        0        0           0          0     0  50000
 gcc_blsp2_ahb_clk                    3        3        0           0          0     0  50000
 gcc_blsp1_sleep_clk                  0        0        0           0          0     0  50000
 gcc_blsp1_ahb_clk                    0        0        0           0          0     0  50000
 gcc_bimc_mss_q6_axi_clk              0        0        0           0          0     0  50000
 gcc_bimc_hmss_axi_clk                0        0        0           0          0     0  50000
 gcc_apss_qdss_tsctr_div8_clk         0        0        0           0          0     0  50000
 gcc_apss_qdss_tsctr_div2_clk         0        0        0           0          0     0  50000
 gcc_aggre1_noc_xo_clk                0        0        0           0          0     0  50000
 sleep_clk                            0        0        0       32764          0     0  50000
 xo_board                             1        1        0    19200000          0     0  50000
    ln_bb_a_clk1                      0        0        0    19200000          0     0  50000
    ln_bb_clk1                        0        0        0    19200000          0     0  50000
    xo                                1        1        0    19200000          0     0  50000
       gcc_rx1_usb2_clkref_clk        0        0        0    19200000          0     0  50000
       gcc_pcie_clkref_clk            0        0        0    19200000          0     0  50000
       gcc_ufs_clkref_clk             0        0        0    19200000          0     0  50000
       gcc_hdmi_clkref_clk            0        0        0    19200000          0     0  50000
       gcc_usb3_clkref_clk            0        0        0    19200000          0     0  50000
       usb3_phy_aux_clk_src           0        0        0     1200000          0     0  50000
          gcc_usb3_phy_aux_clk        0        0        0     1200000          0     0  50000
       usb30_mock_utmi_clk_src        0        0        0    19200000          0     0  50000
          gcc_usb30_mock_utmi_clk     0        0        0    19200000          0     0  50000
       tsif_ref_clk_src               0        0        0    19200000          0     0  50000
          gcc_tsif_ref_clk            0        0        0    19200000          0     0  50000
       sdcc4_apps_clk_src             0        0        0    19200000          0     0  50000
          gcc_sdcc4_apps_clk          0        0        0    19200000          0     0  50000
       sdcc2_apps_clk_src             0        0        0    19200000          0     0  50000
          gcc_sdcc2_apps_clk          0        0        0    19200000          0     0  50000
       pdm2_clk_src                   0        0        0    19200000          0     0  50000
          gcc_pdm2_clk                0        0        0    19200000          0     0  50000
       pcie_aux_clk_src               0        0        0    19200000          0     0  50000
          gcc_pcie_0_aux_clk          0        0        0    19200000          0     0  50000
          gcc_pcie_phy_aux_clk        0        0        0    19200000          0     0  50000
       hmss_rbcpr_clk_src             0        0        0    19200000          0     0  50000
          gcc_hmss_rbcpr_clk          0        0        0    19200000          0     0  50000
       hmss_ahb_clk_src               0        0        0    19200000          0     0  50000
          gcc_hmss_ahb_clk            0        0        0    19200000          0     0  50000
       gpll4                          0        0        0   384000000          0     0  50000
          gpll4_out_test              0        0        0   384000000          0     0  50000
          gpll4_out_odd               0        0        0   384000000          0     0  50000
          gpll4_out_main              0        0        0   384000000          0     0  50000
          gpll4_out_even              0        0        0   384000000          0     0  50000
       gpll3                          0        0        0   921600000          0     0  50000
          gpll3_out_test              0        0        0   921600000          0     0  50000
          gpll3_out_odd               0        0        0   921600000          0     0  50000
          gpll3_out_main              0        0        0   921600000          0     0  50000
          gpll3_out_even              0        0        0   921600000          0     0  50000
       gpll2                          0        0        0  1286400000          0     0  50000
          gpll2_out_test              0        0        0  1286400000          0     0  50000
          gpll2_out_odd               0        0        0  1286400000          0     0  50000
          gpll2_out_main              0        0        0  1286400000          0     0  50000
          gpll2_out_even              0        0        0  1286400000          0     0  50000
       gpll1                          0        0        0  1056000000          0     0  50000
          gpll1_out_test              0        0        0  1056000000          0     0  50000
          gpll1_out_odd               0        0        0  1056000000          0     0  50000
          gpll1_out_main              0        0        0  1056000000          0     0  50000
          gpll1_out_even              0        0        0  1056000000          0     0  50000
       gpll0                          0        0        0   595200000          0     0  50000
          gpll0_out_test              0        0        0   595200000          0     0  50000
          gpll0_out_odd               0        0        0   595200000          0     0  50000
          gpll0_out_main              0        0        0   595200000          0     0  50000
             ufs_unipro_core_clk_src       0        0        0   148800000          0     0  50000
                gcc_ufs_unipro_core_clk       0        0        0   148800000          0     0  50000
             usb30_master_clk_src       0        0        0   119040000          0     0  50000
                gcc_aggre1_usb3_axi_clk       0        0        0   119040000          0     0  50000
                gcc_cfg_noc_usb3_axi_clk       0        0        0   119040000          0     0  50000
                gcc_usb30_master_clk       0        0        0   119040000          0     0  50000
             ufs_axi_clk_src          0        0        0   198400000          0     0  50000
                gcc_aggre1_ufs_axi_clk       0        0        0   198400000          0     0  50000
                gcc_ufs_axi_clk       0        0        0   198400000          0     0  50000
          gpll0_out_even              0        0        0   595200000          0     0  50000
       gp3_clk_src                    0        0        0    19200000          0     0  50000
          gcc_gp3_clk                 0        0        0    19200000          0     0  50000
       gp2_clk_src                    0        0        0    19200000          0     0  50000
          gcc_gp2_clk                 0        0        0    19200000          0     0  50000
       gp1_clk_src                    0        0        0    19200000          0     0  50000
          gcc_gp1_clk                 0        0        0    19200000          0     0  50000
       blsp2_uart3_apps_clk_src       0        0        0    19200000          0     0  50000
          gcc_blsp2_uart3_apps_clk    0        0        0    19200000          0     0  50000
       blsp2_uart2_apps_clk_src       1        1        0     1843200          0     0  50000
          gcc_blsp2_uart2_apps_clk    3        3        0     1843200          0     0  50000
       blsp2_uart1_apps_clk_src       0        0        0    19200000          0     0  50000
          gcc_blsp2_uart1_apps_clk       0        0        0    19200000          0     0  50000
       blsp2_qup6_spi_apps_clk_src       0        0        0    19200000          0     0  50000
          gcc_blsp2_qup6_spi_apps_clk       0        0        0    19200000          0     0  50000
       blsp2_qup6_i2c_apps_clk_src       0        0        0    19200000          0     0  50000
          gcc_blsp2_qup6_i2c_apps_clk       0        0        0    19200000          0     0  50000
       blsp2_qup5_spi_apps_clk_src       0        0        0    19200000          0     0  50000
          gcc_blsp2_qup5_spi_apps_clk       0        0        0    19200000          0     0  50000
       blsp2_qup5_i2c_apps_clk_src       0        0        0    19200000          0     0  50000
          gcc_blsp2_qup5_i2c_apps_clk       0        0        0    19200000          0     0  50000
       blsp2_qup4_spi_apps_clk_src       0        0        0    19200000          0     0  50000
          gcc_blsp2_qup4_spi_apps_clk       0        0        0    19200000          0     0  50000
       blsp2_qup4_i2c_apps_clk_src       0        0        0    19200000          0     0  50000
          gcc_blsp2_qup4_i2c_apps_clk       0        0        0    19200000          0     0  50000
       blsp2_qup3_spi_apps_clk_src       0        0        0    19200000          0     0  50000
          gcc_blsp2_qup3_spi_apps_clk       0        0        0    19200000          0     0  50000
       blsp2_qup3_i2c_apps_clk_src       0        0        0    19200000          0     0  50000
          gcc_blsp2_qup3_i2c_apps_clk       0        0        0    19200000          0     0  50000
       blsp2_qup2_spi_apps_clk_src       0        0        0    19200000          0     0  50000
          gcc_blsp2_qup2_spi_apps_clk       0        0        0    19200000          0     0  50000
       blsp2_qup2_i2c_apps_clk_src       0        0        0    19200000          0     0  50000
          gcc_blsp2_qup2_i2c_apps_clk       0        0        0    19200000          0     0  50000
       blsp2_qup1_spi_apps_clk_src       0        0        0    19200000          0     0  50000
          gcc_blsp2_qup1_spi_apps_clk       0        0        0    19200000          0     0  50000
       blsp2_qup1_i2c_apps_clk_src       0        0        0    19200000          0     0  50000
          gcc_blsp2_qup1_i2c_apps_clk       0        0        0    19200000          0     0  50000
       blsp1_uart3_apps_clk_src       0        0        0    19200000          0     0  50000
          gcc_blsp1_uart3_apps_clk       0        0        0    19200000          0     0  50000
       blsp1_uart2_apps_clk_src       0        0        0    19200000          0     0  50000
          gcc_blsp1_uart2_apps_clk       0        0        0    19200000          0     0  50000
       blsp1_uart1_apps_clk_src       0        0        0    19200000          0     0  50000
          gcc_blsp1_uart1_apps_clk       0        0        0    19200000          0     0  50000
       blsp1_qup6_spi_apps_clk_src       0        0        0    19200000          0     0  50000
          gcc_blsp1_qup6_spi_apps_clk       0        0        0    19200000          0     0  50000
       blsp1_qup6_i2c_apps_clk_src       0        0        0    19200000          0     0  50000
          gcc_blsp1_qup6_i2c_apps_clk       0        0        0    19200000          0     0  50000
       blsp1_qup5_spi_apps_clk_src       0        0        0    19200000          0     0  50000
          gcc_blsp1_qup5_spi_apps_clk       0        0        0    19200000          0     0  50000
       blsp1_qup5_i2c_apps_clk_src       0        0        0    19200000          0     0  50000
          gcc_blsp1_qup5_i2c_apps_clk       0        0        0    19200000          0     0  50000
       blsp1_qup4_spi_apps_clk_src       0        0        0    19200000          0     0  50000
          gcc_blsp1_qup4_spi_apps_clk       0        0        0    19200000          0     0  50000
       blsp1_qup4_i2c_apps_clk_src       0        0        0    19200000          0     0  50000
          gcc_blsp1_qup4_i2c_apps_clk       0        0        0    19200000          0     0  50000
       blsp1_qup3_spi_apps_clk_src       0        0        0    19200000          0     0  50000
          gcc_blsp1_qup3_spi_apps_clk       0        0        0    19200000          0     0  50000
       blsp1_qup3_i2c_apps_clk_src       0        0        0    19200000          0     0  50000
          gcc_blsp1_qup3_i2c_apps_clk       0        0        0    19200000          0     0  50000
       blsp1_qup2_spi_apps_clk_src       0        0        0    19200000          0     0  50000
          gcc_blsp1_qup2_spi_apps_clk       0        0        0    19200000          0     0  50000
       blsp1_qup2_i2c_apps_clk_src       0        0        0    19200000          0     0  50000
          gcc_blsp1_qup2_i2c_apps_clk       0        0        0    19200000          0     0  50000
       blsp1_qup1_spi_apps_clk_src       0        0        0    19200000          0     0  50000
          gcc_blsp1_qup1_spi_apps_clk       0        0        0    19200000          0     0  50000
       blsp1_qup1_i2c_apps_clk_src       0        0        0    19200000          0     0  50000
          gcc_blsp1_qup1_i2c_apps_clk       0        0        0    19200000          0     0  50000


# grep ufs clk_summary
 gcc_ufs_tx_symbol_0_clk              0        0        0           0          0     0  50000
 gcc_ufs_rx_symbol_1_clk              0        0        0           0          0     0  50000
 gcc_ufs_rx_symbol_0_clk              0        0        0           0          0     0  50000
 gcc_ufs_phy_aux_clk                  0        0        0           0          0     0  50000
 gcc_ufs_ice_core_clk                 0        0        0           0          0     0  50000
 gcc_ufs_ahb_clk                      0        0        0           0          0     0  50000
       gcc_ufs_clkref_clk             0        0        0    19200000          0     0  50000
             ufs_unipro_core_clk_src       0        0        0   148800000          0     0  50000
                gcc_ufs_unipro_core_clk       0        0        0   148800000          0     0  50000
             ufs_axi_clk_src          0        0        0   198400000          0     0  50000
                gcc_aggre1_ufs_axi_clk       0        0        0   198400000          0     0  50000
                gcc_ufs_axi_clk       0        0        0   198400000          0     0  50000


I find it surprising that many ufs-related clocks are unparented,
have no rate, and have never been enabled. But that's probably
a red-herring. As Bjorn mentioned, the bootloader probably leaves
all the UFS clocks in the correct state, so the problem must be
elsewhere... Will check the init sequence.

Just for completeness sake, here are the clock parents downstream:

CLOCK=gcc_ufs_ahb_clk			PARENT=None
CLOCK=gcc_ufs_clkref_clk		PARENT=None
CLOCK=gcc_ufs_rx_symbol_0_clk		PARENT=None
CLOCK=gcc_ufs_rx_symbol_1_clk		PARENT=None
CLOCK=gcc_ufs_tx_symbol_0_clk		PARENT=None
CLOCK=gcc_aggre1_ufs_axi_clk		PARENT=ufs_axi_clk_src
CLOCK=gcc_aggre1_ufs_axi_hw_ctl_clk	PARENT=gcc_aggre1_ufs_axi_clk
CLOCK=gcc_ufs_axi_clk			PARENT=ufs_axi_clk_src
CLOCK=gcc_ufs_axi_hw_ctl_clk		PARENT=gcc_ufs_axi_clk
CLOCK=gcc_ufs_ice_core_clk		PARENT=ufs_ice_core_clk_src
CLOCK=gcc_ufs_ice_core_hw_ctl_clk	PARENT=gcc_ufs_ice_core_clk
CLOCK=gcc_ufs_phy_aux_clk		PARENT=ufs_phy_aux_clk_src
CLOCK=gcc_ufs_phy_aux_hw_ctl_clk	PARENT=gcc_ufs_phy_aux_clk
CLOCK=gcc_ufs_unipro_core_clk		PARENT=ufs_unipro_core_clk_src
CLOCK=gcc_ufs_unipro_core_hw_ctl_clk	PARENT=gcc_ufs_unipro_core_clk
CLOCK=ufs_axi_clk_src			PARENT=gpll0_out_main
CLOCK=ufs_ice_core_clk_src		PARENT=gpll0_out_main
CLOCK=ufs_phy_aux_clk_src		PARENT=cxo_clk_src
CLOCK=ufs_unipro_core_clk_src		PARENT=gpll0_out_main

Regards.
Evan Green - Dec. 6, 2018, 4:45 p.m.
On Thu, Dec 6, 2018 at 8:18 AM Marc Gonzalez <marc.w.gonzalez@free.fr> wrote:
>
> On 04/12/2018 18:31, Jeffrey Hugo wrote:
>

I'll throw my random thought into the hopper here. With one particular
brand of UFS part on SDM845 we needed to make sure we banged on the
ufs_reset pin before the device would re-initialize fully. My hunch
says this is not your issue, but it can't hurt to make sure this is
happening.
-Evan
Marc Gonzalez - Dec. 7, 2018, 8:57 a.m.
On 06/12/2018 17:45, Evan Green wrote:

> I'll throw my random thought into the hopper here. With one particular
> brand of UFS part on SDM845 we needed to make sure we banged on the
> ufs_reset pin before the device would re-initialize fully. My hunch
> says this is not your issue, but it can't hurt to make sure this is
> happening.

First of all, thanks for chiming in. I feel I'm close to making this work.

My UFSHC DT node defines:

			resets = <&gcc GCC_UFS_BCR>;
			reset-names = "rst";

If I'm not mistaken, the uhfhc driver should tickle the reset register?
Is the ufs_reset pin something different?

Regards.
Marc Gonzalez - Dec. 7, 2018, 9:29 a.m.
On 07/12/2018 09:57, Marc Gonzalez wrote:

> On 06/12/2018 17:45, Evan Green wrote:
> 
>> I'll throw my random thought into the hopper here. With one particular
>> brand of UFS part on SDM845 we needed to make sure we banged on the
>> ufs_reset pin before the device would re-initialize fully. My hunch
>> says this is not your issue, but it can't hurt to make sure this is
>> happening.
> 
> First of all, thanks for chiming in. I feel I'm close to making this work.
> 
> My UFSHC DT node defines:
> 
> 			resets = <&gcc GCC_UFS_BCR>;
> 			reset-names = "rst";
> 
> If I'm not mistaken, the uhfhc driver should tickle the reset register?
> Is the ufs_reset pin something different?

In fact, I based my UFS stuff on your UFS stuff.
[PATCH v5 0/5] arm64: dts: qcom: sdm845: Add UFS DT nodes

I read the comments in that series, including the fact that the "resets"
property is ignored by the ufshc driver.


Grepping for ufs_reset downstream, I see:

$ git grep -i ufs_reset vendor
vendor:arch/arm/boot/dts/qcom/msm8998-pinctrl.dtsi:                             pins = "ufs_reset";
vendor:arch/arm/boot/dts/qcom/msm8998-pinctrl.dtsi:                              * UFS_RESET driver strengths are having
vendor:arch/arm/boot/dts/qcom/msm8998-pinctrl.dtsi:                              * HDRV value | UFS_RESET | Typical GPIO
vendor:arch/arm/boot/dts/qcom/msm8998-pinctrl.dtsi:                              * POR value for UFS_RESET HDRV is 3 which means
vendor:arch/arm/boot/dts/qcom/msm8998-pinctrl.dtsi:                             pins = "ufs_reset";
vendor:arch/arm/boot/dts/qcom/msm8998-svr20-pinctrl.dtsi:                               pins = "ufs_reset";
vendor:arch/arm/boot/dts/qcom/msm8998-svr20-pinctrl.dtsi:                                * UFS_RESET driver strengths are having
vendor:arch/arm/boot/dts/qcom/msm8998-svr20-pinctrl.dtsi:                                * HDRV value | UFS_RESET | Typical GPIO
vendor:arch/arm/boot/dts/qcom/msm8998-svr20-pinctrl.dtsi:                                * POR value for UFS_RESET HDRV is 3 which means
vendor:arch/arm/boot/dts/qcom/msm8998-svr20-pinctrl.dtsi:                               pins = "ufs_reset";
vendor:drivers/phy/phy-qcom-ufs-qrbtc-v2.c:     writel_relaxed(0x15f, qrbtc_phy->u11_regs + U11_UFS_RESET_REG_OFFSET);
vendor:drivers/phy/phy-qcom-ufs-qrbtc-v2.c:     writel_relaxed(0x0, qrbtc_phy->u11_regs + U11_UFS_RESET_REG_OFFSET);
vendor:drivers/phy/phy-qcom-ufs-qrbtc-v2.h:#define U11_UFS_RESET_REG_OFFSET             PHY_USR(0x4)
vendor:drivers/pinctrl/qcom/pinctrl-msm8998.c:#define UFS_RESET(pg_name, offset)                                \
vendor:drivers/pinctrl/qcom/pinctrl-msm8998.c:  PINCTRL_PIN(153, "UFS_RESET"),
vendor:drivers/pinctrl/qcom/pinctrl-msm8998.c:static const unsigned int ufs_reset_pins[] = { 153 };
vendor:drivers/pinctrl/qcom/pinctrl-msm8998.c:  UFS_RESET(ufs_reset, 0x19d000),

Upstream:

$ git grep -i ufs_reset master
master:Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.txt:                    ufs_reset
master:Documentation/devicetree/bindings/pinctrl/qcom,qcs404-pinctrl.txt:                     ufs_reset
master:drivers/pinctrl/qcom/pinctrl-msm8998.c:#define UFS_RESET(pg_name, offset)                                \
master:drivers/pinctrl/qcom/pinctrl-msm8998.c:  PINCTRL_PIN(153, "UFS_RESET"),
master:drivers/pinctrl/qcom/pinctrl-msm8998.c:static const unsigned int ufs_reset_pins[] = { 153 };
master:drivers/pinctrl/qcom/pinctrl-msm8998.c:  UFS_RESET(ufs_reset, 0x19d000),
master:drivers/pinctrl/qcom/pinctrl-qcs404.c:#define UFS_RESET(pg_name, offset)                         \
master:drivers/pinctrl/qcom/pinctrl-sdm845.c:#define UFS_RESET(pg_name, offset)                         \
master:drivers/pinctrl/qcom/pinctrl-sdm845.c:   PINCTRL_PIN(153, "UFS_RESET"),
master:drivers/pinctrl/qcom/pinctrl-sdm845.c:static const unsigned int ufs_reset_pins[] = { 153 };
master:drivers/pinctrl/qcom/pinctrl-sdm845.c:   UFS_RESET(ufs_reset, 0x99f000),


I need to find the way to make Linux tickle/toggle the ufs_reset pin.

Regards.
Marc Gonzalez - Dec. 7, 2018, 12:10 p.m.
On 06/12/2018 17:45, Evan Green wrote:

> I'll throw my random thought into the hopper here. With one particular
> brand of UFS part on SDM845 we needed to make sure we banged on the
> ufs_reset pin before the device would re-initialize fully. My hunch
> says this is not your issue, but it can't hurt to make sure this is
> happening.

You might be on to something.

Downstream handles the pinctrl nodes, while upstream doesn't.

$ git grep pinc vendor -- drivers/scsi/ufs/
vendor:drivers/scsi/ufs/ufshcd-pltfrm.c:static int ufshcd_parse_pinctrl_info(struct ufs_hba *hba)
vendor:drivers/scsi/ufs/ufshcd-pltfrm.c:        /* Try to obtain pinctrl handle */
vendor:drivers/scsi/ufs/ufshcd-pltfrm.c:        hba->pctrl = devm_pinctrl_get(hba->dev);
vendor:drivers/scsi/ufs/ufshcd-pltfrm.c:        err = ufshcd_parse_pinctrl_info(hba);
vendor:drivers/scsi/ufs/ufshcd-pltfrm.c:                dev_dbg(&pdev->dev, "%s: unable to parse pinctrl data %d\n",
vendor:drivers/scsi/ufs/ufshcd.c:               ret = pinctrl_select_state(hba->pctrl,
vendor:drivers/scsi/ufs/ufshcd.c:                       pinctrl_lookup_state(hba->pctrl, "dev-reset-assert"));
vendor:drivers/scsi/ufs/ufshcd.c:               ret = pinctrl_select_state(hba->pctrl,
vendor:drivers/scsi/ufs/ufshcd.c:                       pinctrl_lookup_state(hba->pctrl, "dev-reset-deassert"));
vendor:drivers/scsi/ufs/ufshcd.h:       struct pinctrl *pctrl;

$ git grep pinc master -- drivers/scsi/ufs/
/* NOTHING */
Evan Green - Dec. 7, 2018, 5:14 p.m.
On Fri, Dec 7, 2018 at 4:10 AM Marc Gonzalez <marc.w.gonzalez@free.fr> wrote:
>
> On 06/12/2018 17:45, Evan Green wrote:
>
> > I'll throw my random thought into the hopper here. With one particular
> > brand of UFS part on SDM845 we needed to make sure we banged on the
> > ufs_reset pin before the device would re-initialize fully. My hunch
> > says this is not your issue, but it can't hurt to make sure this is
> > happening.
>
> You might be on to something.
>
> Downstream handles the pinctrl nodes, while upstream doesn't.
>
> $ git grep pinc vendor -- drivers/scsi/ufs/
> vendor:drivers/scsi/ufs/ufshcd-pltfrm.c:static int ufshcd_parse_pinctrl_info(struct ufs_hba *hba)
> vendor:drivers/scsi/ufs/ufshcd-pltfrm.c:        /* Try to obtain pinctrl handle */
> vendor:drivers/scsi/ufs/ufshcd-pltfrm.c:        hba->pctrl = devm_pinctrl_get(hba->dev);
> vendor:drivers/scsi/ufs/ufshcd-pltfrm.c:        err = ufshcd_parse_pinctrl_info(hba);
> vendor:drivers/scsi/ufs/ufshcd-pltfrm.c:                dev_dbg(&pdev->dev, "%s: unable to parse pinctrl data %d\n",
> vendor:drivers/scsi/ufs/ufshcd.c:               ret = pinctrl_select_state(hba->pctrl,
> vendor:drivers/scsi/ufs/ufshcd.c:                       pinctrl_lookup_state(hba->pctrl, "dev-reset-assert"));
> vendor:drivers/scsi/ufs/ufshcd.c:               ret = pinctrl_select_state(hba->pctrl,
> vendor:drivers/scsi/ufs/ufshcd.c:                       pinctrl_lookup_state(hba->pctrl, "dev-reset-deassert"));
> vendor:drivers/scsi/ufs/ufshcd.h:       struct pinctrl *pctrl;
>
> $ git grep pinc master -- drivers/scsi/ufs/
> /* NOTHING */

We did this by abusing the "init" pinctrl state, which I think gets
handled automagically. In our board file we have something like this
(forgive the paste butchering):
&ufshc1 {
status = "okay";
pinctrl-names = "init", "default";
pinctrl-0 = <&ufs_dev_reset_assert>;
pinctrl-1 = <&ufs_dev_reset_deassert>;

vcc-supply = <&src_pp2950_l20a>;
vcc-max-microamp = <600000>;
};


&tlmm {
ufs_dev_reset_assert: ufs_dev_reset_assert {
config {
pins = "ufs_reset";
bias-pull-down; /* default: pull down */
drive-strength = <8>; /* default: 3.1 mA */
output-low; /* active low reset */
};
};

ufs_dev_reset_deassert: ufs_dev_reset_deassert {
config {
pins = "ufs_reset";
bias-pull-down; /* default: pull down */
drive-strength = <8>;
output-high; /* active low reset */
};
};
};

Patch

diff --git a/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi b/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi
index b4276da1fb0d..cc35086422b4 100644
--- a/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi
@@ -241,3 +241,26 @@ 
 		};
 	};
 };
+
+&ufshc {
+	status = "ok";
+/***	vdd-hba-supply = <&gcc UFS_GDSC>;	-EPROBE_DEFER ***/
+	vdd-hba-fixed-regulator;
+	vcc-supply = <&vreg_l20a_2p95>;
+	vccq-supply = <&vreg_l26a_1p2>;
+	vccq2-supply = <&vreg_s4a_1p8>;
+	vcc-max-microamp = <750000>;
+	vccq-max-microamp = <560000>;
+	vccq2-max-microamp = <750000>;
+};
+
+&ufsphy {
+	status = "ok";
+	vdda-phy-supply = <&vreg_l1a_0p875>;
+	vdda-pll-supply = <&vreg_l2a_1p2>;
+	vddp-ref-clk-supply = <&vreg_l26a_1p2>;
+	vdda-phy-max-microamp = <51400>;
+	vdda-pll-max-microamp = <14600>;
+	vddp-ref-clk-max-microamp = <100>;
+	vddp-ref-clk-always-on;
+};
diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
index d291b4713c33..b5b2b05bc782 100644
--- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
@@ -264,6 +264,11 @@ 
 		rpm_requests: rpm-requests {
 			compatible = "qcom,rpm-msm8998";
 			qcom,glink-channels = "rpm_requests";
+
+			rpmcc: qcom,rpmcc {
+				compatible = "qcom,rpmcc-msm8998";
+				#clock-cells = <1>;
+			};
 		};
 	};
 
@@ -686,5 +691,75 @@ 
 			redistributor-stride = <0x0 0x20000>;
 			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 		};
+
+		ufshc: ufshc@1da4000 {
+			compatible = "qcom,msm8998-ufshc", "qcom,ufshc",
+				     "jedec,ufs-2.0";
+			reg = <0x1da4000 0x2500>;
+			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+			phys = <&ufsphy_lanes>;
+			phy-names = "ufsphy";
+			lanes-per-direction = <2>;
+			power-domains = <&gcc UFS_GDSC>;
+
+			clock-names =
+				"core_clk",
+				"bus_aggr_clk",
+				"iface_clk",
+				"core_clk_unipro",
+				"core_clk_ice",
+				"ref_clk",
+				"tx_lane0_sync_clk",
+				"rx_lane0_sync_clk",
+				"rx_lane1_sync_clk";
+			clocks =
+				<&gcc GCC_UFS_AXI_CLK>,
+				<&gcc GCC_AGGRE1_UFS_AXI_CLK>,
+				<&gcc GCC_UFS_AHB_CLK>,
+				<&gcc GCC_UFS_UNIPRO_CORE_CLK>,
+				<&gcc GCC_UFS_ICE_CORE_CLK>,
+				<&rpmcc 0>,
+				<&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
+				<&gcc GCC_UFS_RX_SYMBOL_0_CLK>,
+				<&gcc GCC_UFS_RX_SYMBOL_1_CLK>;
+			freq-table-hz =
+				<50000000 200000000>,
+				<0 0>,
+				<0 0>,
+				<37500000 150000000>,
+				<75000000 300000000>,
+				<0 0>,
+				<0 0>,
+				<0 0>,
+				<0 0>;
+
+			resets = <&gcc GCC_UFS_BCR>;
+			reset-names = "rst";
+
+			status = "disabled";
+		};
+
+		ufsphy: phy@1da7000 {
+			compatible = "qcom,sdm845-qmp-ufs-phy";
+			reg = <0x1da7000 0x18c>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			clock-names = "ref", "ref_aux";
+			clocks =
+				<&gcc GCC_UFS_CLKREF_CLK>,
+				<&gcc GCC_UFS_PHY_AUX_CLK>;
+
+			status = "disabled";
+
+			ufsphy_lanes: lanes@1da7400 {
+				reg = <0x1da7400 0x108>,
+				      <0x1da7600 0x1e0>,
+				      <0x1da7c00 0x1dc>,
+				      <0x1da7800 0x108>,
+				      <0x1da7a00 0x1e0>;
+				#phy-cells = <0>;
+			};
+		};
 	};
 };
diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c
index 850c02a52248..12a0a2d6ec7b 100644
--- a/drivers/clk/qcom/clk-smd-rpm.c
+++ b/drivers/clk/qcom/clk-smd-rpm.c
@@ -611,10 +611,25 @@  static const struct rpm_smd_clk_desc rpm_clk_msm8996 = {
 	.num_clks = ARRAY_SIZE(msm8996_clks),
 };
 
+/* msm8998 */
+#define LN_BB_CLK1_ID 0x1
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, ln_bb_clk1, ln_bb_a_clk1, LN_BB_CLK1_ID);
+
+static struct clk_smd_rpm *msm8998_clks[] = {
+	[0] = &msm8998_ln_bb_clk1,
+	[1] = &msm8998_ln_bb_a_clk1,
+};
+
+static const struct rpm_smd_clk_desc rpm_clk_msm8998 = {
+	.clks = msm8998_clks,
+	.num_clks = ARRAY_SIZE(msm8998_clks),
+};
+
 static const struct of_device_id rpm_smd_clk_match_table[] = {
 	{ .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916 },
 	{ .compatible = "qcom,rpmcc-msm8974", .data = &rpm_clk_msm8974 },
 	{ .compatible = "qcom,rpmcc-msm8996", .data = &rpm_clk_msm8996 },
+	{ .compatible = "qcom,rpmcc-msm8998", .data = &rpm_clk_msm8998 },
 	{ }
 };
 MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table);
diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c
index 9f0ae403d5f5..4fc1502cab5c 100644
--- a/drivers/clk/qcom/gcc-msm8998.c
+++ b/drivers/clk/qcom/gcc-msm8998.c
@@ -1972,6 +1972,7 @@  static struct clk_branch gcc_hmss_dvm_bus_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_hmss_dvm_bus_clk",
+			.flags = CLK_IS_CRITICAL,
 			.ops = &clk_branch2_ops,
 		},
 	},
@@ -2015,6 +2016,7 @@  static struct clk_branch gcc_lpass_at_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_lpass_at_clk",
+			.flags = CLK_IS_CRITICAL,
 			.ops = &clk_branch2_ops,
 		},
 	},
@@ -2401,7 +2403,7 @@  static struct clk_branch gcc_ufs_phy_aux_clk = {
 
 static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
 	.halt_reg = 0x75014,
-	.halt_check = BRANCH_HALT,
+	.halt_check = BRANCH_HALT_SKIP,
 	.clkr = {
 		.enable_reg = 0x75014,
 		.enable_mask = BIT(0),
@@ -2414,7 +2416,7 @@  static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
 
 static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
 	.halt_reg = 0x7605c,
-	.halt_check = BRANCH_HALT,
+	.halt_check = BRANCH_HALT_SKIP,
 	.clkr = {
 		.enable_reg = 0x7605c,
 		.enable_mask = BIT(0),
@@ -2427,7 +2429,7 @@  static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
 
 static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
 	.halt_reg = 0x75010,
-	.halt_check = BRANCH_HALT,
+	.halt_check = BRANCH_HALT_SKIP,
 	.clkr = {
 		.enable_reg = 0x75010,
 		.enable_mask = BIT(0),
@@ -2541,6 +2543,76 @@  static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
 	},
 };
 
+static struct clk_branch gcc_hdmi_clkref_clk = {
+	.halt_reg = 0x88000,
+	.clkr = {
+		.enable_reg = 0x88000,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gcc_hdmi_clkref_clk",
+			.parent_names = (const char *[]){ "xo" },
+			.num_parents = 1,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_ufs_clkref_clk = {
+	.halt_reg = 0x88004,
+	.clkr = {
+		.enable_reg = 0x88004,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gcc_ufs_clkref_clk",
+			.parent_names = (const char *[]){ "xo" },
+			.num_parents = 1,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_usb3_clkref_clk = {
+	.halt_reg = 0x88008,
+	.clkr = {
+		.enable_reg = 0x88008,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gcc_usb3_clkref_clk",
+			.parent_names = (const char *[]){ "xo" },
+			.num_parents = 1,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_pcie_clkref_clk = {
+	.halt_reg = 0x8800c,
+	.clkr = {
+		.enable_reg = 0x8800c,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gcc_pcie_clkref_clk",
+			.parent_names = (const char *[]){ "xo" },
+			.num_parents = 1,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_rx1_usb2_clkref_clk = {
+	.halt_reg = 0x88014,
+	.clkr = {
+		.enable_reg = 0x88014,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gcc_rx1_usb2_clkref_clk",
+			.parent_names = (const char *[]){ "xo" },
+			.num_parents = 1,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
 static struct gdsc pcie_0_gdsc = {
 	.gdscr = 0x6b004,
 	.gds_hw_ctrl = 0x0,
@@ -2733,6 +2805,11 @@  static struct clk_regmap *gcc_msm8998_clocks[] = {
 	[USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
 	[USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
 	[USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
+	[GCC_HDMI_CLKREF_CLK] = &gcc_hdmi_clkref_clk.clkr,
+	[GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr,
+	[GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr,
+	[GCC_PCIE_CLKREF_CLK] = &gcc_pcie_clkref_clk.clkr,
+	[GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr,
 };
 
 static struct gdsc *gcc_msm8998_gdscs[] = {
@@ -2742,25 +2819,25 @@  static struct gdsc *gcc_msm8998_gdscs[] = {
 };
 
 static const struct qcom_reset_map gcc_msm8998_resets[] = {
-	[GCC_BLSP1_QUP1_BCR] = { 0x102400 },
-	[GCC_BLSP1_QUP2_BCR] = { 0x110592 },
-	[GCC_BLSP1_QUP3_BCR] = { 0x118784 },
-	[GCC_BLSP1_QUP4_BCR] = { 0x126976 },
-	[GCC_BLSP1_QUP5_BCR] = { 0x135168 },
-	[GCC_BLSP1_QUP6_BCR] = { 0x143360 },
-	[GCC_BLSP2_QUP1_BCR] = { 0x155648 },
-	[GCC_BLSP2_QUP2_BCR] = { 0x163840 },
-	[GCC_BLSP2_QUP3_BCR] = { 0x172032 },
-	[GCC_BLSP2_QUP4_BCR] = { 0x180224 },
-	[GCC_BLSP2_QUP5_BCR] = { 0x188416 },
-	[GCC_BLSP2_QUP6_BCR] = { 0x196608 },
-	[GCC_PCIE_0_BCR] = { 0x438272 },
-	[GCC_PDM_BCR] = { 0x208896 },
-	[GCC_SDCC2_BCR] = { 0x81920 },
-	[GCC_SDCC4_BCR] = { 0x90112 },
-	[GCC_TSIF_BCR] = { 0x221184 },
-	[GCC_UFS_BCR] = { 0x479232 },
-	[GCC_USB_30_BCR] = { 0x61440 },
+	[GCC_BLSP1_QUP1_BCR] = { 0x19000 },
+	[GCC_BLSP1_QUP2_BCR] = { 0x1b000 },
+	[GCC_BLSP1_QUP3_BCR] = { 0x1d000 },
+	[GCC_BLSP1_QUP4_BCR] = { 0x1f000 },
+	[GCC_BLSP1_QUP5_BCR] = { 0x21000 },
+	[GCC_BLSP1_QUP6_BCR] = { 0x23000 },
+	[GCC_BLSP2_QUP1_BCR] = { 0x26000 },
+	[GCC_BLSP2_QUP2_BCR] = { 0x28000 },
+	[GCC_BLSP2_QUP3_BCR] = { 0x2a000 },
+	[GCC_BLSP2_QUP4_BCR] = { 0x2c000 },
+	[GCC_BLSP2_QUP5_BCR] = { 0x2e000 },
+	[GCC_BLSP2_QUP6_BCR] = { 0x30000 },
+	[GCC_PCIE_0_BCR] = { 0x6b000 },
+	[GCC_PDM_BCR] = { 0x33000 },
+	[GCC_SDCC2_BCR] = { 0x14000 },
+	[GCC_SDCC4_BCR] = { 0x16000 },
+	[GCC_TSIF_BCR] = { 0x36000 },
+	[GCC_UFS_BCR] = { 0x75000 },
+	[GCC_USB_30_BCR] = { 0xf000 },
 };
 
 static const struct regmap_config gcc_msm8998_regmap_config = {
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8998.h b/include/dt-bindings/clock/qcom,gcc-msm8998.h
index 58a242e656b1..b3448800980a 100644
--- a/include/dt-bindings/clock/qcom,gcc-msm8998.h
+++ b/include/dt-bindings/clock/qcom,gcc-msm8998.h
@@ -180,6 +180,11 @@ 
 #define USB30_MASTER_CLK_SRC					163
 #define USB30_MOCK_UTMI_CLK_SRC					164
 #define USB3_PHY_AUX_CLK_SRC					165
+#define GCC_USB3_CLKREF_CLK					166
+#define GCC_HDMI_CLKREF_CLK					167
+#define GCC_UFS_CLKREF_CLK					168
+#define GCC_PCIE_CLKREF_CLK					169
+#define GCC_RX1_USB2_CLKREF_CLK					170
 
 #define PCIE_0_GDSC						0
 #define UFS_GDSC						1