Patchwork [v3,16/17] SUPPORT.md: Add limits RFC

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Submitter George Dunlap
Date Nov. 22, 2017, 7:20 p.m.
Message ID <20171122192024.21187-16-george.dunlap@citrix.com>
Download mbox | patch
Permalink /patch/388329/
State New
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George Dunlap - Nov. 22, 2017, 7:20 p.m.
Signed-off-by: George Dunlap <george.dunlap@citrix.com>
---
Changes since v2:
- Update memory limits for PV guests

CC: Ian Jackson <ian.jackson@citrix.com>
CC: Wei Liu <wei.liu2@citrix.com>
CC: Andrew Cooper <andrew.cooper3@citrix.com>
CC: Jan Beulich <jbeulich@suse.com>
CC: Stefano Stabellini <sstabellini@kernel.org>
CC: Konrad Wilk <konrad.wilk@oracle.com>
CC: Tim Deegan <tim@xen.org>
---
 SUPPORT.md | 68 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 67 insertions(+), 1 deletion(-)

Patch

diff --git a/SUPPORT.md b/SUPPORT.md
index aa58fb0de3..72be1414a1 100644
--- a/SUPPORT.md
+++ b/SUPPORT.md
@@ -62,6 +62,58 @@  for the definitions of the support status levels etc.
 
 Extension to the GICv3 interrupt controller to support MSI.
 
+## Limits/Host
+
+### CPUs
+
+    Limit, x86: 4095
+    Limit, ARM32: 8
+    Limit, ARM64: 128
+
+Note that for x86, very large number of cpus may not work/boot,
+but we will still provide security support
+
+### x86/RAM
+
+    Limit, x86: 123TiB
+    Limit, ARM32: 16GiB
+    Limit, ARM64: 5TiB
+
+## Limits/Guest
+
+### Virtual CPUs
+
+    Limit, x86 PV: 8192
+    Limit-security, x86 PV: 32
+    Limit, x86 HVM: 128
+    Limit-security, x86 HVM: 32
+    Limit, ARM32: 8
+    Limit, ARM64: 128
+
+### Virtual RAM
+
+    Limit-security, x86 PV 64-bit: 2047GiB
+    Limit-security, x86 PV 32-bit: 168GiB (see below)
+    Limit-security, x86 HVM: 1.5TiB
+    Limit, ARM32: 16GiB
+    Limit, ARM64: 1TiB
+
+Note that there are no theoretical limits to 64-bit PV or HVM guest sizes
+other than those determined by the processor architecture.
+
+All 32-bit PV guest memory must be under 168GiB;
+this means the total memory for all 32-bit PV guests cannot exced 168GiB.
+On larger hosts, this limit is 128GiB.
+
+### Event Channel 2-level ABI
+
+    Limit, 32-bit: 1024
+    Limit, 64-bit: 4096
+
+### Event Channel FIFO ABI
+
+    Limit: 131072
+
 ## Guest Type
 
 ### x86/PV
@@ -634,7 +686,7 @@  that covers the DMA of the device to be passed through.
 
     Status: Supported, with caveats
 
-No support for QEMU backends in a 16K or 64K domain.
+No support for QEMU backends bin a 16K or 64K domain.
 
 ### ARM: Guest Devicetree support
 
@@ -736,6 +788,20 @@  If support differs based on implementation
 (for instance, x86 / ARM, Linux / QEMU / FreeBSD),
 one line for each set of implementations will be listed.
 
+### Limit-security
+
+For size limits.
+This figure shows the largest configuration which will receive
+security support.
+It is generally determined by the maximum amount that is regularly tested.
+This limit will only be listed explicitly
+if it is different than the theoretical limit.
+
+### Limit
+
+This figure shows a theoretical size limit.
+This does not mean that such a large configuration will actually work.
+
 ## Definition of Status labels
 
 Each Status value corresponds to levels of security support,