Patchwork [1/2] x86/svm: Add virtual GIF feature definition

login
register
mail settings
Submitter brian.woods@amd.com
Date Nov. 16, 2017, 3:32 p.m.
Message ID <20171116153203.71358-2-brian.woods@amd.com>
Download mbox | patch
Permalink /patch/385179/
State New
Headers show

Comments

brian.woods@amd.com - Nov. 16, 2017, 3:32 p.m.
Add support for enabling the virtual GIF feature.

Signed-off-by: Brian Woods <brian.woods@amd.com>
---
 xen/include/asm-x86/hvm/svm/svm.h  | 2 ++
 xen/include/asm-x86/hvm/svm/vmcb.h | 6 ++++--
 2 files changed, 6 insertions(+), 2 deletions(-)

Patch

diff --git a/xen/include/asm-x86/hvm/svm/svm.h b/xen/include/asm-x86/hvm/svm/svm.h
index 0956f860ef..ec1eda6a3e 100644
--- a/xen/include/asm-x86/hvm/svm/svm.h
+++ b/xen/include/asm-x86/hvm/svm/svm.h
@@ -64,6 +64,7 @@  extern u32 svm_feature_flags;
 #define SVM_FEATURE_FLUSHBYASID    6 /* TLB flush by ASID support */
 #define SVM_FEATURE_DECODEASSISTS  7 /* Decode assists support */
 #define SVM_FEATURE_PAUSEFILTER   10 /* Pause intercept filter support */
+#define SVM_FEATURE_VGIF          16 /* Virtual GIF */
 
 #define cpu_has_svm_feature(f) test_bit(f, &svm_feature_flags)
 #define cpu_has_svm_npt       cpu_has_svm_feature(SVM_FEATURE_NPT)
@@ -72,6 +73,7 @@  extern u32 svm_feature_flags;
 #define cpu_has_svm_nrips     cpu_has_svm_feature(SVM_FEATURE_NRIPS)
 #define cpu_has_svm_cleanbits cpu_has_svm_feature(SVM_FEATURE_VMCBCLEAN)
 #define cpu_has_svm_decode    cpu_has_svm_feature(SVM_FEATURE_DECODEASSISTS)
+#define cpu_has_svm_vgif      cpu_has_svm_feature(SVM_FEATURE_VGIF)
 #define cpu_has_pause_filter  cpu_has_svm_feature(SVM_FEATURE_PAUSEFILTER)
 #define cpu_has_tsc_ratio     cpu_has_svm_feature(SVM_FEATURE_TSCRATEMSR)
 
diff --git a/xen/include/asm-x86/hvm/svm/vmcb.h b/xen/include/asm-x86/hvm/svm/vmcb.h
index 01ce20b0bd..595cfcf57b 100644
--- a/xen/include/asm-x86/hvm/svm/vmcb.h
+++ b/xen/include/asm-x86/hvm/svm/vmcb.h
@@ -325,12 +325,14 @@  typedef union
     {
         u64 tpr:          8;
         u64 irq:          1;
-        u64 rsvd0:        7;
+        u64 vgif:         1;
+        u64 rsvd0:        6;
         u64 prio:         4;
         u64 ign_tpr:      1;
         u64 rsvd1:        3;
         u64 intr_masking: 1;
-        u64 rsvd2:        7;
+        u64 vgif_enable:  1;
+        u64 rsvd2:        6;
         u64 vector:       8;
         u64 rsvd3:       24;
     } fields;