Patchwork [for-4.10] x86/cpuid: Minor fixups missed from previous work

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Submitter Andrew Cooper
Date Nov. 3, 2017, 5:35 p.m.
Message ID <1509730550-1618-1-git-send-email-andrew.cooper3@citrix.com>
Download mbox | patch
Permalink /patch/377923/
State New
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Andrew Cooper - Nov. 3, 2017, 5:35 p.m.
* Add more feature names to ./xen-cpuid
 * Vertically align the magic comments in cpufeatureset.h

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
CC: Jan Beulich <JBeulich@suse.com>
CC: Ian Jackson <Ian.Jackson@eu.citrix.com>
CC: Wei Liu <wei.liu2@citrix.com>
CC: Julien Grall <julien.grall@arm.com>

This is a nice-to-have for Xen 4.10.  It is very low risk, as the functional
changes are restricted to debug utilities only.
---
 tools/misc/xen-cpuid.c                      | 15 ++++++++++-----
 xen/include/public/arch-x86/cpufeatureset.h |  4 ++--
 2 files changed, 12 insertions(+), 7 deletions(-)
Jan Beulich - Nov. 6, 2017, 12:35 p.m.
>>> On 03.11.17 at 18:35, <andrew.cooper3@citrix.com> wrote:
> * Add more feature names to ./xen-cpuid
>  * Vertically align the magic comments in cpufeatureset.h
> 
> Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>

Acked-by: Jan Beulich <jbeulich@suse.com>
Wei Liu - Nov. 6, 2017, 1:55 p.m.
On Mon, Nov 06, 2017 at 05:35:10AM -0700, Jan Beulich wrote:
>  >>> On 03.11.17 at 18:35, <andrew.cooper3@citrix.com> wrote:
> > * Add more feature names to ./xen-cpuid
> >  * Vertically align the magic comments in cpufeatureset.h
> > 
> > Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
> 
> Acked-by: Jan Beulich <jbeulich@suse.com>
> 
> 

Acked-by: Wei Liu <wei.liu2@citrix.com>
Julien Grall - Nov. 8, 2017, 12:31 p.m.
Hi,

On 03/11/17 17:35, Andrew Cooper wrote:
>   * Add more feature names to ./xen-cpuid
>   * Vertically align the magic comments in cpufeatureset.h
> 
> Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
> ---
> CC: Jan Beulich <JBeulich@suse.com>
> CC: Ian Jackson <Ian.Jackson@eu.citrix.com>
> CC: Wei Liu <wei.liu2@citrix.com>
> CC: Julien Grall <julien.grall@arm.com>
> 
> This is a nice-to-have for Xen 4.10.  It is very low risk, as the functional
> changes are restricted to debug utilities only.

Release-acked-by: Julien Grall <julien.grall@linaro.org>

Cheers,

> ---
>   tools/misc/xen-cpuid.c                      | 15 ++++++++++-----
>   xen/include/public/arch-x86/cpufeatureset.h |  4 ++--
>   2 files changed, 12 insertions(+), 7 deletions(-)
> 
> diff --git a/tools/misc/xen-cpuid.c b/tools/misc/xen-cpuid.c
> index 106be0f..0831f75 100644
> --- a/tools/misc/xen-cpuid.c
> +++ b/tools/misc/xen-cpuid.c
> @@ -95,7 +95,7 @@ static const char *str_7b0[32] =
>       [ 0] = "fsgsbase", [ 1] = "tsc-adj",
>       [ 2] = "sgx",      [ 3] = "bmi1",
>       [ 4] = "hle",      [ 5] = "avx2",
> -    [ 6] = "REZ",      [ 7] = "smep",
> +    [ 6] = "fdp_exn",  [ 7] = "smep",
>       [ 8] = "bmi2",     [ 9] = "erms",
>       [10] = "invpcid",  [11] = "rtm",
>       [12] = "pqm",      [13] = "depfpp",
> @@ -121,23 +121,28 @@ static const char *str_Da1[32] =
>   static const char *str_7c0[32] =
>   {
>       [ 0] = "prechwt1", [ 1] = "avx512vbmi",
> -    [ 2] = "REZ",      [ 3] = "pku",
> +    [ 2] = "umip",     [ 3] = "pku",
>       [ 4] = "ospke",
>   
>       [5 ... 13] = "REZ",
>   
>       [14] = "avx512_vpopcntdq",
>   
> -    [15 ... 31] = "REZ",
> +    [15 ... 21] = "REZ",
> +
> +    [22] = "rdpid",
> +
> +    [23 ... 31] = "REZ",
>   };
>   
>   static const char *str_e7d[32] =
>   {
>       [0 ... 7] = "REZ",
>   
> -    [ 8] = "itsc",
> +    [ 8] = "itsc",     [ 9] = "REZ",
> +    [10] = "efro",
>   
> -    [9 ... 31] = "REZ",
> +    [11 ... 31] = "REZ",
>   };
>   
>   static const char *str_e8b[32] =
> diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h
> index 0ee3ea3..be6da8e 100644
> --- a/xen/include/public/arch-x86/cpufeatureset.h
> +++ b/xen/include/public/arch-x86/cpufeatureset.h
> @@ -239,8 +239,8 @@ XEN_CPUFEATURE(EFRO,          7*32+10) /*   APERF/MPERF Read Only interface */
>   XEN_CPUFEATURE(CLZERO,        8*32+ 0) /*A  CLZERO instruction */
>   
>   /* Intel-defined CPU features, CPUID level 0x00000007:0.edx, word 9 */
> -XEN_CPUFEATURE(AVX512_4VNNIW, 9*32+ 2) /*A AVX512 Neural Network Instructions */
> -XEN_CPUFEATURE(AVX512_4FMAPS, 9*32+ 3) /*A AVX512 Multiply Accumulation Single Precision */
> +XEN_CPUFEATURE(AVX512_4VNNIW, 9*32+ 2) /*A  AVX512 Neural Network Instructions */
> +XEN_CPUFEATURE(AVX512_4FMAPS, 9*32+ 3) /*A  AVX512 Multiply Accumulation Single Precision */
>   
>   #endif /* XEN_CPUFEATURE */
>   
>

Patch

diff --git a/tools/misc/xen-cpuid.c b/tools/misc/xen-cpuid.c
index 106be0f..0831f75 100644
--- a/tools/misc/xen-cpuid.c
+++ b/tools/misc/xen-cpuid.c
@@ -95,7 +95,7 @@  static const char *str_7b0[32] =
     [ 0] = "fsgsbase", [ 1] = "tsc-adj",
     [ 2] = "sgx",      [ 3] = "bmi1",
     [ 4] = "hle",      [ 5] = "avx2",
-    [ 6] = "REZ",      [ 7] = "smep",
+    [ 6] = "fdp_exn",  [ 7] = "smep",
     [ 8] = "bmi2",     [ 9] = "erms",
     [10] = "invpcid",  [11] = "rtm",
     [12] = "pqm",      [13] = "depfpp",
@@ -121,23 +121,28 @@  static const char *str_Da1[32] =
 static const char *str_7c0[32] =
 {
     [ 0] = "prechwt1", [ 1] = "avx512vbmi",
-    [ 2] = "REZ",      [ 3] = "pku",
+    [ 2] = "umip",     [ 3] = "pku",
     [ 4] = "ospke",
 
     [5 ... 13] = "REZ",
 
     [14] = "avx512_vpopcntdq",
 
-    [15 ... 31] = "REZ",
+    [15 ... 21] = "REZ",
+
+    [22] = "rdpid",
+
+    [23 ... 31] = "REZ",
 };
 
 static const char *str_e7d[32] =
 {
     [0 ... 7] = "REZ",
 
-    [ 8] = "itsc",
+    [ 8] = "itsc",     [ 9] = "REZ",
+    [10] = "efro",
 
-    [9 ... 31] = "REZ",
+    [11 ... 31] = "REZ",
 };
 
 static const char *str_e8b[32] =
diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h
index 0ee3ea3..be6da8e 100644
--- a/xen/include/public/arch-x86/cpufeatureset.h
+++ b/xen/include/public/arch-x86/cpufeatureset.h
@@ -239,8 +239,8 @@  XEN_CPUFEATURE(EFRO,          7*32+10) /*   APERF/MPERF Read Only interface */
 XEN_CPUFEATURE(CLZERO,        8*32+ 0) /*A  CLZERO instruction */
 
 /* Intel-defined CPU features, CPUID level 0x00000007:0.edx, word 9 */
-XEN_CPUFEATURE(AVX512_4VNNIW, 9*32+ 2) /*A AVX512 Neural Network Instructions */
-XEN_CPUFEATURE(AVX512_4FMAPS, 9*32+ 3) /*A AVX512 Multiply Accumulation Single Precision */
+XEN_CPUFEATURE(AVX512_4VNNIW, 9*32+ 2) /*A  AVX512 Neural Network Instructions */
+XEN_CPUFEATURE(AVX512_4FMAPS, 9*32+ 3) /*A  AVX512 Multiply Accumulation Single Precision */
 
 #endif /* XEN_CPUFEATURE */